Vishesh Mishra

Orcid: 0000-0001-6867-4587

According to our database1, Vishesh Mishra authored at least 26 papers between 2020 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Dual-Mode Rounding Algorithms and Hardware for Posit-Based DNN Training: The Future of Mixed Precision Frameworks.
ACM Trans. Embed. Comput. Syst., January, 2026

PowerShift: Leveraging Power-Aware Weight Approximations for Neural Network Acceleration.
Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

SilentBite: A Novel LLM-based framework for Automated Hardware Trojan Insertion.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
SATGuard: SAT-driven Countermeasures for Protecting Approximate Circuits from Hardware Trojan.
ACM Trans. Embed. Comput. Syst., November, 2025

Novel hybrid probabilistic-statistical error metrics for approximate adders.
J. Syst. Archit., 2025

Breaking PCB-Chain: A Side Channel Assisted Attack on IoT-Friendly Blockchain Mining.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2025

SERA-Float: A Soft Error Resilient Approximate Floating-Point Computing Format.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

Dual-Mode Rounding Algorithms and Hardware for Posit-based DNN Training: The Future of Mixed Precision Frameworks.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2025

2024
CPU-Doctor: when a device's heart-beat can be an acoustic side-channel disassembler.
J. Cryptogr. Eng., September, 2024

Security Implications of Approximation: A Study of Trojan Attacks on Approximate Adders and Multipliers.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Sorting Attacks Resilient Authentication Protocol for CMOS Image Sensor Based PUF.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2024

2023
VADF: Versatile Approximate Data Formats for Energy-Efficient Computing.
ACM Trans. Embed. Comput. Syst., October, 2023

B2T: The Third Logical Value of a Bit.
IACR Cryptol. ePrint Arch., 2023

DARK-Adders: Digital Hardware Trojan Attack on Block-based Approximate Adders.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

Novel, Configurable Approximate Floating-point Multipliers for Error-Resilient Applications.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Aiding to Multimedia Accelerators: A Hardware Design for Efficient Rounding of Binary Floating Point Numbers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
VMEO: Vector Modeling Errors and Operands for Approximate adders.
IACR Cryptol. ePrint Arch., 2022

On the Performance and Optimization of HAPS Assisted Dual-Hop Hybrid RF/FSO System.
IEEE Access, 2022

EFCSA: An Efficient Carry Speculative Approximate Adder with Rectification.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

AxLEAP: Enabling Low-Power Approximations Through Unified Power Format.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

ART-MAC: Approximate Rounding and Truncation based MAC Unit for Fault-Tolerant Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

MEGA-MAC: A Merged Accumulation based Approximate MAC Unit for Error Resilient Applications.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
Performance Analysis of HAPS Assisted Dual-Hop Hybrid RF/FSO System.
Proceedings of the 94th IEEE Vehicular Technology Conference, 2021

SAM: A Segmentation Based Approximate Multiplier for Error Tolerant Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
An Approximate Carry Estimating Simultaneous Adder with Rectification.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020


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