Sahibia Kaur Vohra
Orcid: 0000-0001-5592-9552
According to our database1,
Sahibia Kaur Vohra
authored at least 8 papers
between 2021 and 2024.
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Bibliography
2024
Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons.
Integr., March, 2024
2023
Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse.
IEEE Trans. Very Large Scale Integr. Syst., 2023
Analysing Mismatch effect of CMOS Neurons in Spiking Neural Network with Winner-take-all Mechanism.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
2022
CMOS Circuit Implementation of Spiking Neural Network for Pattern Recognition Using On-chip Unsupervised STDP Learning.
CoRR, 2022
2021
Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021
Full CMOS Implementation of Bidirectional Associative Memory Neural Network with Analog Memristive Synapse.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Analysis of Parasitics on CMOS based Memristor Crossbar Array for Neuromorphic Systems.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
A Robust Training Signal Generator for Trainable Memristive Digital to Analog Converter.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021