Sailesh K. Rao

According to our database1, Sailesh K. Rao authored at least 13 papers between 1984 and 1997.

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Bibliography

1997
100BASE-T2: a new standard for 100 Mb/s Ethernet transmission over voice-grade cables.
IEEE Commun. Mag., 1997

100BASE-T2: 100 Mbit/s Ethernet over Two Pairs of Category-3 Cabling.
Proceedings of the 1997 IEEE International Conference on Communications: Towards the Knowledge Millennium, 1997

1995
The ATM physical layer.
Comput. Commun. Rev., 1995

1994
Application Specific Memories for ATM Packet Switching.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1992
The Rectilinear Steiner Arborescence Problem.
Algorithmica, 1992

1990
On the Analysis of Synchronous Computing Systems.
SIAM J. Comput., 1990

A design environment for high performance VLSI signal processing.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1989
Communication reduction for distributed sparse matrix factorization on a processor mesh.
Proceedings of the Proceedings Supercomputing '89, Reno, NV, USA, November 12-17, 1989, 1989

The matrix transform chip.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1988
Regular iterative algorithms and their implementation on processor arrays.
Proc. IEEE, 1988

1987
Array architectures for iterative algorithms.
Proc. IEEE, 1987

Design of minimal-degree compensators with assignable poles or structure.
Autom., 1987

1984
Pipelined orthogonal digital lattice filters.
Proceedings of the IEEE International Conference on Acoustics, 1984


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