Sailesh Kumar

According to our database1, Sailesh Kumar authored at least 17 papers between 2002 and 2013.

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Bibliography

2013
A few bits are enough - ASIC friendly Regular Expression matching for high speed network security systems.
Proceedings of the 2013 21st IEEE International Conference on Network Protocols, 2013

2011
Non-crypto Hardware Hash Functions for High Performance Networking ASICs.
Proceedings of the 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2011

2010
Smart memory.
Proceedings of the 2010 IEEE Hot Chips 22 Symposium, Stanford, CA, USA, August 22-24, 2010, 2010

2009
Divide and discriminate: algorithm for deterministic and fast hash lookups.
Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009

2008
Exploiting Locality to Ameliorate Packet Queue Contention and Serialization.
J. Instr. Level Parallelism, 2008

Peacock Hashing: Deterministic and Updatable Hashing for High Performance Networking.
Proceedings of the INFOCOM 2008. 27th IEEE International Conference on Computer Communications, 2008

2007
Supercharging planetlab: a high performance, multi-application, overlay network platform.
Proceedings of the ACM SIGCOMM 2007 Conference on Applications, 2007

HEXA: Compact Data Structures for Faster Packet Processing.
Proceedings of the IEEE International Conference on Network Protocols, 2007

Curing regular expressions matching algorithms from insomnia, amnesia, and acalculia.
Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2007

2006
Algorithms to accelerate multiple regular expressions matching for deep packet inspection.
Proceedings of the ACM SIGCOMM 2006 Conference on Applications, 2006

Advanced algorithms for fast and scalable deep packet inspection.
Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2006

CAMP: fast and efficient IP lookup architecture.
Proceedings of the 2006 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2006

2005
Addressing Queuing Bottlenecks at High Speeds.
Proceedings of the 13th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2005), 2005

Design of Randomized Multichannel Packet Storage for High Performance Routers.
Proceedings of the 13th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2005), 2005

Optimizing memory bandwidth of a multi-channel packet buffer.
Proceedings of the Global Telecommunications Conference, 2005. GLOBECOM '05, St. Louis, Missouri, USA, 28 November, 2005

Segmented hash: an efficient hash table implementation for high performance networking subsystems.
Proceedings of the 2005 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2005

2002
A Fault Modeling Technique to Test Memory BIST Algorithms.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002


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