Saketh Gajawada

According to our database, Saketh Gajawada authored at least 6 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2025

LUTAccel: Look-up-Table Based Vector Systolic Accelerator on FPGAs.

Aashish Kumar Tiwary, Saketh Gajawada, Jay Shah, Nanditha Rao

Proceedings of the 26th International Symposium on Quality Electronic Design, 2025

Design of Hardware-Efficient Inexact Multiplier Using Evolutionary Algorithm Factored by Multi-Variate Approximation.

Dantu Nandini Devi, Saketh Gajawada, Madhav Rao

Proceedings of the 26th International Symposium on Quality Electronic Design, 2025

2024

FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC.

Saketh Gajawada, Aryan Gupta, Kailash Prasad, Joycee Mekie

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

MOHSKM: Meta-Heuristic Optimization Driven Hardware-Efficient Heterogeneous-Split Karatsuba Multipliers for Large-Bit Operations.

Saketh Gajawada, Dantu Nandini Devi, Madhav Rao

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

FPGA-based Hardware Software Co-design to Accelerate Brain Tumour Segmentation.

Vinay Rayapati, Gogireddy Ravi Kiran Reddy, Gandi Ajay Kumar, Saketh Gajawada, Sanampudi Gopala Krishna Reddy, Nanditha Rao

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

HAHMF: Heuristic-Augmented Asymmetric Heterogeneous Splitting for Hardware Efficient Multipliers Framework.

Saketh Gajawada, Dantu Nandini Devi, Madhav Rao

Proceedings of the 27th Euromicro Conference on Digital System Design, 2024