Kailash Prasad

Orcid: 0000-0002-4873-7728

According to our database1, Kailash Prasad authored at least 16 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
SDR-PUF: Sequence-Dependent Reconfigurable SRAM PUF with an Exponential CRP Space.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Hybrid CMOS-Memristor Logic for Boosting the Power-Efficiency in Error Tolerant Applications.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy.
ACM Trans. Archit. Code Optim., June, 2023

Fast and Robust Sense Amplifier for Digital In Memory Computing.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

Process Variation Resilient Current-Domain Analog In Memory Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

PVC-RAM:Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Hardware-Software Codesign of DNN Accelerators Using Approximate Posit Multipliers.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Impact of Operand Ordering in Approximate Multiplication in Neural Network and Image Processing Applications.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022

FastMem: A Fast Architecture-aware Memory Layout Design.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Analysis of Word Line Shaping Techniques for In-Memory Computing in SRAMs.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020
SEDAAF: FPGA Based Single Exact Dual Approximate Adders for Approximate Processors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

FPAD: A Multistage Approximation Methodology for Designing Floating Point Approximate Dividers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020


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