Sanchita Saha Ray

Orcid: 0000-0001-7921-1916

According to our database1, Sanchita Saha Ray authored at least 10 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2023
${O(N)}$O(N) Memory-Free Hardware Architecture for Burrows-Wheeler Transform.
IEEE Trans. Computers, July, 2023

k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

2022
Worst Case O(N) Comparison-Free Hardware Sorting Engine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Memory Efficient Hash-Based Longest Prefix Matching Architecture With Zero False +ve and Nearly Zero False -ve Rate for IP Processing.
IEEE Trans. Computers, 2022

2020
A stochastic operational matrix method for numerical solutions of mixed stochastic Volterra-Fredholm integral equations.
Int. J. Wavelets Multiresolution Inf. Process., 2020

2019
Stochastic operational matrix of Chebyshev wavelets for solving multi-dimensional stochastic Itô-Volterra integral equations.
Int. J. Wavelets Multiresolution Inf. Process., 2019

A Comparison-free Hardware Sorting Engine.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018
A Fine-grained Integrated IP Lookup Engine for Multigigabit IP Processing.
Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2018

2016
An SRAM-based novel hardware architecture for longest prefix matching for IP route lookup.
Photonic Netw. Commun., 2016

2015
SRAM based longest prefix matching approach for multigigabit IP processing.
Proceedings of the 2015 IEEE International Conference on Advanced Networks and Telecommuncations Systems, 2015


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