Sandeep K. Gupta

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Bibliography

2009

Body Area Networking: Technology and Applications.

[BibT_eX]

[DOI]

IEEE J. Sel. Areas Commun., 2009

2007

ERTG: A test generator for error-rate testing.

[BibT_eX]

[DOI]

Shideh Shahidi

Sandeep K. Gupta

Proceedings of the 2007 IEEE International Test Conference, 2007

Accurate modeling and fault simulation of Byzantine resistive bridges.

[BibT_eX]

[DOI]

Hugo Cheung

Sandeep K. Gupta

Proceedings of the 25th International Conference on Computer Design, 2007

2006

Estimating Error Rate during Self-Test via One's Counting.

[BibT_eX]

[DOI]

Shideh Shahidi

Sandeep K. Gupta

Proceedings of the 2006 IEEE International Test Conference, 2006

1998

Efficient BIST TPG design and test set compaction via input reduction.

[BibT_eX]

[DOI]

Chih-Ang Chen

Sandeep K. Gupta

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Efficient BIST TPG design and test set compaction for delay testing via input reduction.

[BibT_eX]

[DOI]

Chih-Ang Chen

Sandeep K. Gupta

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1996

Design of efficient BIST test pattern generators for delay testing.

[BibT_eX]

[DOI]

Chih-Ang Chen

Sandeep K. Gupta

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation.

[BibT_eX]

[DOI]

Hugo Cheung

Sandeep K. Gupta

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995

Zero Aliasing for Modeled Faults.

[BibT_eX]

[DOI]

Mody Lempel

Sandeep K. Gupta

IEEE Trans. Computers, 1995

A Methodology to Design Efficient BIST Test Pattern Generators.

[BibT_eX]

[DOI]

Chih-Ang Chen

Sandeep K. Gupta

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Sandeep K. Gupta

Bibliography

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