Chih-Ang Chen

According to our database, Chih-Ang Chen authored at least 8 papers between 1994 and 1998.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1998

Efficient BIST TPG design and test set compaction via input reduction.

Chih-Ang Chen, Sandeep K. Gupta

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Efficient BIST TPG design and test set compaction for delay testing via input reduction.

Chih-Ang Chen, Sandeep K. Gupta

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1996

Design of efficient BIST test pattern generators for delay testing.

Chih-Ang Chen, Sandeep K. Gupta

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms.

Chih-Ang Chen, Sandeep K. Gupta

IEEE Trans. Computers, 1996

A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts.

Chih-Ang Chen, Sandeep K. Gupta

Proceedings of the 33st Conference on Design Automation, 1996

1995

A Methodology to Design Efficient BIST Test Pattern Generators.

Chih-Ang Chen, Sandeep K. Gupta

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994

Low power state assignment targeting two-and multi-level logic implementations.

Chi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

BIST Test Pattern Generators for Stuck-Open and Delay Testing.

Chih-Ang Chen, Sandeep K. Gupta

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994