Sanket Tavarageri

According to our database1, Sanket Tavarageri authored at least 17 papers between 2010 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
PolyDL: Polyhedral Optimizations for Creation of High-performance DL Primitives.
ACM Trans. Archit. Code Optim., 2021

AI Powered Compiler Techniques for DL Code Optimization.
CoRR, 2021

2020
PolyScientist: Automatic Loop Transformations Combined with Microkernels for Optimization of Deep Learning Primitives.
CoRR, 2020

2019
Automatic Model Parallelism for Deep Neural Networks with Compiler and Hardware Support.
CoRR, 2019

Categorization of Program Regions for Agile Compilation using Machine Learning and Hardware Support.
CoRR, 2019

2018
A Data Analytics Framework for Aggregate Data Analysis.
CoRR, 2018

2017
A medical price prediction system using hierarchical decision trees.
Proceedings of the 2017 IEEE International Conference on Big Data (IEEE BigData 2017), 2017

2016
Architecting and Programming a Hardware-Incoherent Multiprocessor Cache Hierarchy.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

Compiler Support for Software Cache Coherence.
Proceedings of the 23rd IEEE International Conference on High Performance Computing, 2016

2015
Automatic cluster parallelization and minimizing communication via selective data replication.
Proceedings of the 2015 IEEE High Performance Extreme Computing Conference, 2015

2014
A Tale of Three Runtimes.
CoRR, 2014

Compiler-assisted detection of transient memory errors.
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 2014

PWCET: Power-Aware Worst Case Execution Time Analysis.
Proceedings of the 43rd International Conference on Parallel Processing Workshops, 2014

2013
Adaptive parallel tiled code generation and accelerated auto-tuning.
Int. J. High Perform. Comput. Appl., 2013

A Compiler Analysis to Determine Useful Cache Size for Energy Efficiency.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

2011
Dynamic selection of tile sizes.
Proceedings of the 18th International Conference on High Performance Computing, 2011

2010
Parameterized tiling revisited.
Proceedings of the CGO 2010, 2010


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