Saravana Manivannan

According to our database, Saravana Manivannan authored at least 9 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining.

Shanthi Pavan, Saravana Manivannan, Nishanth Basavaraj

IEEE J. Solid State Circuits, January, 2024

2022

Simplified Simulation and Measurement of the Signal Transfer Function of a Continuous-Time Pipelined Analog-to-Digital Converter.

Nishanth Basavaraj, Saravana Manivannan, Shanthi Pavan

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Analysis of RC Time-Constant Variations in Continuous-Time Pipelined ADCs.

Shanthi Pavan, Saravana Manivannan

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Improved Multistage Continuous-Time Pipelined Analog-to-Digital Converters and the Implicit Decimation Property.

Saravana Manivannan, Shanthi Pavan

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Analysis of Flash ADC Loading on the Performance of a Continuous-Time Pipelined ADC.

Chaitanya Kumar, Saravana Manivannan, Shanthi Pavan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2020

Improved Continuous-Time Delta-Sigma Modulators With Embedded Active Filtering.

Saravana Manivannan, Shanthi Pavan

IEEE Trans. Circuits Syst., 2020

2019

Degradation of Alias Rejection in Continuous-Time Bandpass Delta-Sigma Converters due to Weak Loop Filter Nonlinearities.

Saravana Manivannan, Shanthi Pavan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

Degradation of Alias Rejection in Continuous-Time Delta-Sigma Modulators by Weak Loop-Filter Nonlinearities.

Saravana Manivannan, Shanthi Pavan

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 1 MHz bandwidth, filtering continuous-time delta-sigma ADC with 36 dBFS out-of-band IIP3 and 76 dB SNDR.

Saravana Manivannan, Shanthi Pavan

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018