Shanthi Pavan

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019

Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators.

[BibT_eX]

[DOI]

Raviteja Theertham

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Improved Offline Calibration of DAC Mismatch Errors in Delta-Sigma Data Converters.

[BibT_eX]

[DOI]

Raviteja Theertham

IEEE Trans. Circuits Syst. II Express Briefs, 2019

An Alternative Approach to Bode's Noise Theorem.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Analysis and Design of Cyclic Switched-Capacitor DC-DC Converters.

[BibT_eX]

[DOI]

Kishalay Datta

Vinod Menezes

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2019

A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth.

[BibT_eX]

[DOI]

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Simplified Analysis of Total Integrated Noise in Passive Switched-Capacitor and N-Path Filters.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Degradation of Alias Rejection in Continuous-Time Bandpass Delta-Sigma Converters due to Weak Loop Filter Nonlinearities.

[BibT_eX]

[DOI]

Saravana Manivannan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 265μW Continuous-Time 1-2 MASH ADC Achieving 100.6 dB SNDR in a 24 kHz Bandwidth.

[BibT_eX]

[DOI]

Sujith Billa

Suhas Dixit

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018

Generalized Analysis of High-Order Switch-RC N-Path Mixers/Filters Using the Adjoint Network.

[BibT_eX]

[DOI]

Eric A. M. Klumperink

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Analysis of the Effect of Source Capacitance and Inductance on $N$ -Path Mixers and Filters.

[BibT_eX]

[DOI]

Eric A. M. Klumperink

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Improved Chopping in Continuous-Time Delta-Sigma Converters Using FIR Feedback and N-Path Techniques.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Degradation of Alias Rejection in Continuous-Time Delta-Sigma Modulators by Weak Loop-Filter Nonlinearities.

[BibT_eX]

[DOI]

Saravana Manivannan

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

What Architecture Should I Choose for my Continuous-Time Delta-Sigma Modulator?

[BibT_eX]

[DOI]

Siddharth Baskaran

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting.

[BibT_eX]

[DOI]

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

Practical design and simulation techniques for continuous-time ΔΣ converters.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

Finite-impulse-response (FIR) feedback in continuous-time delta-sigma converters.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A 1 MHz bandwidth, filtering continuous-time delta-sigma ADC with 36 dBFS out-of-band IIP3 and 76 dB SNDR.

[BibT_eX]

[DOI]

Saravana Manivannan

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017

Simplified Unified Analysis of Switched-RC Passive Mixers, Samplers, and N-Path Filters Using the Adjoint Network.

[BibT_eX]

[DOI]

Eric A. M. Klumperink

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Analysis of Chopped Integrators, and Its Application to Continuous-Time Delta-Sigma Modulator Design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Design and Analysis of an 8 mW, 1 GHz Span, Passive Spectrum Scanner With >+31 dBm Out-of-Band IIP3 Using Periodically Time-Varying Circuit Components.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

Analysis and Design of Continuous-Time Delta-Sigma Converters Incorporating Chopping.

[BibT_eX]

[DOI]

Sujith Billa

IEEE J. Solid State Circuits, 2017

On linear periodically time varying (LPTV) systems with modulated inputs, and their application to smoothing filters.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Design of Continuous-Time ΔΣ Modulators With Dual Switched-Capacitor Return-to-Zero DACs.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2016

A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition.

[BibT_eX]

[DOI]

Kamlesh Singh

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Demystifying Time Varying Circuits and Systems.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts.

[BibT_eX]

[DOI]

Sujith Billa

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Continuous-time ΔΣ modulators with dual switched capacitor resistor DACs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Outgoing Editorial.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Next-Generation Delta-Sigma Converters: Trends and Perspectives.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Guest Editorial: Next-Generation Delta-Sigma Converters.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Programmable analog pulse shaping for ultra-wideband applications.

[BibT_eX]

[DOI]

Naga Rajesh

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 10 Gbps eye opening monitor in 65nm CMOS.

[BibT_eX]

[DOI]

Sandeep Krishnan

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC Conference 2015, 2015

2014

Interreciprocity in Linear Periodically Time-Varying Networks With Sampled Outputs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Simplified Analysis and Simulation of the STF, NTF, and Noise in Continuous-Time ΔΣ Modulators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Continuous-Time Delta-Sigma Modulator Design Using the Method of Moments.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Incoming Editorial.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Guest Editorial Special Section on the 2013 IEEE International Symposium on Circuits and Systems (ISCAS 2013).

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Characterization Techniques for High Speed Oversampled Data Converters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2014

Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming.

[BibT_eX]

[DOI]

Naga Rajesh

IEEE J. Solid State Circuits, 2014

Design Techniques for Continuous-Time ΔΣ Modulators With Embedded Active Filtering.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2014

29.1 A 5mW CT ΔΣ ADC with embedded 2nd-order active filter and VGA achieving 82dB DR in 2MHz BW.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Efficient estimation of noise and signal transfer functions of a continuous-time ΣΔ modulator.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Guest Editorial Special Section on the 2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012).

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Guest Editorial: Special Section on the 2012 IEEE Custom Integrated Circuits Conference (CICC 2012).

[BibT_eX]

[DOI]

John W. M. Rogers

Vikas Chandra

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A Time-Domain Perspective of the Signal Transfer Function of a Continuous-Time ΔΣ Modulator.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2013

Continuous-Time ΔΣ Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC.

[BibT_eX]

[DOI]

Timir Nandi

Karthikeya Boominathan

IEEE J. Solid State Circuits, 2013

Improved characterization of high speed continuous-time ΔΣ modulators using a duobinary test interface.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A lumped component programmable delay element for Ultra-Wideband beamforming.

[BibT_eX]

[DOI]

Naga Rajesh

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

Device Noise in Continuous-Time Oversampling Converters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Guest Editorial Special Section on the 2011 IEEE Custom Integrated Circuits Conference (CICC 2011).

[BibT_eX]

[DOI]

Chip-Hong Chang

Howard C. Luong

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 16 MHz BW 75 dB DR CT ΔΣ ADC Compensated for More Than One Cycle Excess Loop Delay.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2012

Design Techniques for Wideband Single-Bit Continuous-Time Delta Sigma Modulators With FIR Feedback DACs.

[BibT_eX]

[DOI]

Pradeep Shettigar

IEEE J. Solid State Circuits, 2012

Analysis and Design of a High Speed Continuous-time ΔΣ Modulator Using the Assisted Opamp Technique.

[BibT_eX]

[DOI]

Muthusubramaniam Venkatesan

IEEE J. Solid State Circuits, 2012

A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS.

[BibT_eX]

[DOI]

Pradeep Shettigar

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Little-known features of well-known creatures.

[BibT_eX]

[DOI]

Un-Ku Moon

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Device noise in continuous-time ΔΣ modulators with Switched-Capacitor feedback DACs.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC.

[BibT_eX]

[DOI]

Timir Nandi

Karthikeya Boominathan

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

On Continuous-Time DeltaSigma Modulators With Return-to-Open DACs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

Alias Rejection of Continuous-Time DeltaSigma Modulators With Switched-Capacitor Feedback DACs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Active-RC Filters Using the Gm-Assisted OTA-RC Technique.

[BibT_eX]

[DOI]

Siva V. Thyagarajan

IEEE J. Solid State Circuits, 2011

The inconvenient truth about alias rejection in continuous time ΔΣ converters.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 4mW 1 GS/s continuous-time ΔΣ modulator with 15.6MHz bandwidth and 67 dB dynamic range.

[BibT_eX]

[DOI]

Muthusubramanian Venkateswaran

Proceedings of the 37th European Solid-State Circuits Conference, 2011

A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time DeltaSigma Modulators.

[BibT_eX]

[DOI]

Vikas Singh

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Systematic Design Centering of Continuous Time Oversampling Converters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Efficient Simulation of Weak Nonlinearities in Continuous-Time Oversampling Converters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

Understanding weak loop filter nonlinearities in continuous time ΔΣ converters.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low distortion active filters using the Gm-assisted OTA-RC technique.

[BibT_eX]

[DOI]

Siva V. Thyagarajan

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

Widely Programmable High-Frequency Active RC Filters in CMOS Technology.

[BibT_eX]

[DOI]

Venkata Prasadu

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Negative Feedback System and Circuit Design.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Automatic Tuning of Time Constants in Single Bit Continuous-time Delta-sigma Modulators.

[BibT_eX]

[DOI]

Saurabh Saxena

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Digitally Assisted Baseband Filter with 9MHz Bandwidth and 0.3 dB IQ Mismatch for a WLAN Receiver Chain.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A 110µW single bit audio continuous-time oversampled converter with 92.5 db dynamic range.

[BibT_eX]

[DOI]

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008

Power and Area-Efficient Adaptive Equalization at Microwave Frequencies.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

A Power Optimized Continuous-Time ΔΣ ADC for Audio Applications.

[BibT_eX]

[DOI]

Ramalingam Pandarinathan

IEEE J. Solid State Circuits, 2008

Oversampling Analog-to-Digital Converter Design.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Power and area efficient high speed analog adaptive equalization.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 20.7mW continuous-time ΔΣ modulator with 15MHz bandwidth and 70 dB dynamic range.

[BibT_eX]

[DOI]

Karthikeyan Reddy

Proceedings of the ESSCIRC 2008, 2008

2007

Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta-Sigma Modulators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Fundamental Limitations of Continuous-Time Delta-Sigma Modulators Due to Clock Jitter.

[BibT_eX]

[DOI]

Karthikeyan Reddy

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Analysis and Design of Singly Terminated Transmission-Line FIR Adaptive Equalizers.

[BibT_eX]

[DOI]

Rajesh Tiruvuru

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Automatic Tuning of Time Constants in Continuous-Time Delta-Sigma Modulators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Efficient Design Centering of High-Frequency Integrated Continuous-Time Filters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Accurate Characterization of Integrated Continuous-Time Filters.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2007

Singly Terminated & Bi-Transversal Transmission Line Filters for High Speed Adaptive Equalization.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design Centering High Frequency Integrated Continuous-Time Filters.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A 90μW 15-bit ΔΣ ADC for digital audio.

[BibT_eX]

[DOI]

Ramalingam Pandarinathan

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

A low power 44-300 MHz programmable active-RC filter in 0.18 μm CMOS.

[BibT_eX]

[DOI]

Venkata Prasadu

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Nonidealities in traveling wave and transversal FIR filters operating at microwave frequencies.

[BibT_eX]

[DOI]

Shankar Shivappa

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A Distortion Compensating Flash Analog-to-Digital Conversion Technique.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2006

System Aspects of Analog to Digital Converter Designs.

[BibT_eX]

[DOI]

Prakash Easwaran

C. Srinivasan

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Transmission line based FIR structures for high speed adaptive equalization.

[BibT_eX]

[DOI]

Rajesh Tiruvuru

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Rapid Simulation of Current Steering Digital-to-Analog Converters using Verilog-A.

[BibT_eX]

[DOI]

Murali Shanmugasundaram

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A Technique for Accurate Frequency Response Measurement of Integrated Continuous-Time Filters.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

Analysis of traveling wave and transversal analog adaptive equalizers.

[BibT_eX]

[DOI]

Shankar Shivappa

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

Continuous-time integrated FIR filters at microwave frequencies.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2004

A fixed transconductance bias technique for CMOS analog integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2001

A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000

Widely programmable high-frequency continuous-time filters in digital CMOS technology.

[BibT_eX]

[DOI]

Yannis P. Tsividis

Krishnaswamy Nagaraj

IEEE J. Solid State Circuits, 2000

A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2000

1999

Modeling of accumulation MOS capacitors for analog design in digital VLSI processes.

[BibT_eX]

[DOI]