Shanthi Pavan

Orcid: 0000-0002-6938-8491

According to our database1, Shanthi Pavan authored at least 135 papers between 1999 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2018, "For contributions to delta sigma modulators and analog filters".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
On the Use of FIR Feedback in Bandpass Delta-Sigma Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining.
IEEE J. Solid State Circuits, January, 2024

Systematic Development of CMOS PTAT Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Digital Reconstruction in Continuous-Time Pipelined Analog-to-Digital Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Power-Noise Trade-Offs in Continuous-Time Pipelined ADCs and Active Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023

Reciprocity and Inter-Reciprocity: A Tutorial - Part II: Linear Periodically Time-Varying Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023

Reciprocity and Inter-Reciprocity: A Tutorial - Part I: Linear Time-Invariant Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023

Bandpass $\Delta \Sigma$ Modulators with FIR Feedback.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 13.5 mW Decimator for a 20 MHz bandwidth CTΔΣ Modulator using poly-phase decomposition techniques.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022
Alias Rejection in CT Delta-Sigma ADCs Using Virtual-Ground-Switched Resistor Feedback.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Systematic Development of CMOS Fixed-Transconductance Bias Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Simplified Simulation and Measurement of the Signal Transfer Function of a Continuous-Time Pipelined Analog-to-Digital Converter.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Analysis of RC Time-Constant Variations in Continuous-Time Pipelined ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Improved Multistage Continuous-Time Pipelined Analog-to-Digital Converters and the Implicit Decimation Property.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Design of High-Resolution Continuous-Time Delta-Sigma Data Converters With Dual Return-to-Open DACs.
IEEE J. Solid State Circuits, 2022

Analysis of Flash ADC Loading on the Performance of a Continuous-Time Pipelined ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 0.37mm<sup>2</sup> 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2<sup>nd</sup>-order Vector-Quantizer DEM.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
Continuous-Time Pipelined Analog-to-Digital Converters: A Mini-Tutorial.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Continuous-Time Incremental Delta-Sigma Modulators With FIR Feedback.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Analysis and Design of a 20-MHz Bandwidth Continuous-Time Delta-Sigma Modulator With Time-Interleaved Virtual-Ground-Switched FIR Feedback.
IEEE J. Solid State Circuits, 2021

A 28.5µW All-Analog Voice-Activity Detector.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Improved Continuous-Time Delta-Sigma Modulators With Embedded Active Filtering.
IEEE Trans. Circuits Syst., 2020

Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density.
IEEE J. Solid State Circuits, 2020

Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta-Sigma Modulator.
IEEE J. Solid State Circuits, 2020

16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

A 20 MHz Bandwidth Continuous-Time Delta-Sigma ADC Achieving 82.1 dB SNDR and > 00 dB SFDR Using a Time-Interleaved Virtual-Ground-Switched FIR Feedback DAC.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Improved Offline Calibration of DAC Mismatch Errors in Delta-Sigma Data Converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

An Alternative Approach to Bode's Noise Theorem.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Analysis and Design of Cyclic Switched-Capacitor DC-DC Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting.
IEEE J. Solid State Circuits, 2019

A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Simplified Analysis of Total Integrated Noise in Passive Switched-Capacitor and N-Path Filters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Degradation of Alias Rejection in Continuous-Time Bandpass Delta-Sigma Converters due to Weak Loop Filter Nonlinearities.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 265μW Continuous-Time 1-2 MASH ADC Achieving 100.6 dB SNDR in a 24 kHz Bandwidth.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
Generalized Analysis of High-Order Switch-RC N-Path Mixers/Filters Using the Adjoint Network.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Analysis of the Effect of Source Capacitance and Inductance on $N$ -Path Mixers and Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Improved Chopping in Continuous-Time Delta-Sigma Converters Using FIR Feedback and N-Path Techniques.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Degradation of Alias Rejection in Continuous-Time Delta-Sigma Modulators by Weak Loop-Filter Nonlinearities.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Continuous-Time Delta-Sigma Modulators With Time-Interleaved FIR Feedback.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

What Architecture Should I Choose for my Continuous-Time Delta-Sigma Modulator?
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

Practical design and simulation techniques for continuous-time ΔΣ converters.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

Finite-impulse-response (FIR) feedback in continuous-time delta-sigma converters.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A 1 MHz bandwidth, filtering continuous-time delta-sigma ADC with 36 dBFS out-of-band IIP3 and 76 dB SNDR.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
Simplified Unified Analysis of Switched-RC Passive Mixers, Samplers, and N-Path Filters Using the Adjoint Network.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Analysis of Chopped Integrators, and Its Application to Continuous-Time Delta-Sigma Modulator Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Design and Analysis of an 8 mW, 1 GHz Span, Passive Spectrum Scanner With >+31 dBm Out-of-Band IIP3 Using Periodically Time-Varying Circuit Components.
IEEE J. Solid State Circuits, 2017

A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD.
IEEE J. Solid State Circuits, 2017

Analysis and Design of Continuous-Time Delta-Sigma Converters Incorporating Chopping.
IEEE J. Solid State Circuits, 2017

On linear periodically time varying (LPTV) systems with modulated inputs, and their application to smoothing filters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Design of Continuous-Time ΔΣ Modulators With Dual Switched-Capacitor Return-to-Zero DACs.
IEEE J. Solid State Circuits, 2016

A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Demystifying Time Varying Circuits and Systems.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Continuous-time ΔΣ modulators with dual switched capacitor resistor DACs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Outgoing Editorial.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Next-Generation Delta-Sigma Converters: Trends and Perspectives.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Guest Editorial: Next-Generation Delta-Sigma Converters.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Programmable analog pulse shaping for ultra-wideband applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 10 Gbps eye opening monitor in 65nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A continuous-time ΔΣ modulator with 91dB dynamic range in a 2 MHz signal bandwidth using a dual switched-capacitor return-to-zero DAC.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
Interreciprocity in Linear Periodically Time-Varying Networks With Sampled Outputs.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Simplified Analysis and Simulation of the STF, NTF, and Noise in Continuous-Time ΔΣ Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Continuous-Time Delta-Sigma Modulator Design Using the Method of Moments.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Incoming Editorial.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Guest Editorial Special Section on the 2013 IEEE International Symposium on Circuits and Systems (ISCAS 2013).
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Characterization Techniques for High Speed Oversampled Data Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback.
IEEE J. Solid State Circuits, 2014

Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming.
IEEE J. Solid State Circuits, 2014

Design Techniques for Continuous-Time ΔΣ Modulators With Embedded Active Filtering.
IEEE J. Solid State Circuits, 2014

29.1 A 5mW CT ΔΣ ADC with embedded 2<sup>nd</sup>-order active filter and VGA achieving 82dB DR in 2MHz BW.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Efficient estimation of noise and signal transfer functions of a continuous-time ΣΔ modulator.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Guest Editorial Special Section on the 2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012).
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Guest Editorial: Special Section on the 2012 IEEE Custom Integrated Circuits Conference (CICC 2012).
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A Time-Domain Perspective of the Signal Transfer Function of a Continuous-Time ΔΣ Modulator.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Continuous-Time ΔΣ Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC.
IEEE J. Solid State Circuits, 2013

Improved characterization of high speed continuous-time ΔΣ modulators using a duobinary test interface.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A lumped component programmable delay element for Ultra-Wideband beamforming.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Device Noise in Continuous-Time Oversampling Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Guest Editorial Special Section on the 2011 IEEE Custom Integrated Circuits Conference (CICC 2011).
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 16 MHz BW 75 dB DR CT ΔΣ ADC Compensated for More Than One Cycle Excess Loop Delay.
IEEE J. Solid State Circuits, 2012

Design Techniques for Wideband Single-Bit Continuous-Time Delta Sigma Modulators With FIR Feedback DACs.
IEEE J. Solid State Circuits, 2012

Analysis and Design of a High Speed Continuous-time ΔΣ Modulator Using the Assisted Opamp Technique.
IEEE J. Solid State Circuits, 2012

A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Little-known features of well-known creatures.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Device noise in continuous-time ΔΣ modulators with Switched-Capacitor feedback DACs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
On Continuous-Time DeltaSigma Modulators With Return-to-Open DACs.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Alias Rejection of Continuous-Time DeltaSigma Modulators With Switched-Capacitor Feedback DACs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Active-RC Filters Using the Gm-Assisted OTA-RC Technique.
IEEE J. Solid State Circuits, 2011

The inconvenient truth about alias rejection in continuous time ΔΣ converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 4mW 1 GS/s continuous-time ΔΣ modulator with 15.6MHz bandwidth and 67 dB dynamic range.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A 16MHz BW 75dB DR CT ΔΣ ADC compensated for more than one cycle excess loop delay.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time DeltaSigma Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Systematic Design Centering of Continuous Time Oversampling Converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Efficient Simulation of Weak Nonlinearities in Continuous-Time Oversampling Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique.
IEEE J. Solid State Circuits, 2010

Understanding weak loop filter nonlinearities in continuous time ΔΣ converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low distortion active filters using the Gm-assisted OTA-RC technique.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
Widely Programmable High-Frequency Active <i>RC</i> Filters in CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Negative Feedback System and Circuit Design.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Automatic Tuning of Time Constants in Single Bit Continuous-time Delta-sigma Modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Digitally Assisted Baseband Filter with 9MHz Bandwidth and 0.3 dB IQ Mismatch for a WLAN Receiver Chain.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A 110µW single bit audio continuous-time oversampled converter with 92.5 db dynamic range.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
Power and Area-Efficient Adaptive Equalization at Microwave Frequencies.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

A Power Optimized Continuous-Time ΔΣ ADC for Audio Applications.
IEEE J. Solid State Circuits, 2008

Oversampling Analog-to-Digital Converter Design.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Power and area efficient high speed analog adaptive equalization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A 20.7mW continuous-time ΔΣ modulator with 15MHz bandwidth and 70 dB dynamic range.
Proceedings of the ESSCIRC 2008, 2008

2007
Analysis of Integrator Nonlinearity in a Class of Continuous-Time Delta-Sigma Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Fundamental Limitations of Continuous-Time Delta-Sigma Modulators Due to Clock Jitter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Analysis and Design of Singly Terminated Transmission-Line FIR Adaptive Equalizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Automatic Tuning of Time Constants in Continuous-Time Delta-Sigma Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Efficient Design Centering of High-Frequency Integrated Continuous-Time Filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Accurate Characterization of Integrated Continuous-Time Filters.
IEEE J. Solid State Circuits, 2007

Singly Terminated & Bi-Transversal Transmission Line Filters for High Speed Adaptive Equalization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design Centering High Frequency Integrated Continuous-Time Filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A 90μW 15-bit ΔΣ ADC for digital audio.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

A low power 44-300 MHz programmable active-RC filter in 0.18 μm CMOS.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Nonidealities in traveling wave and transversal FIR filters operating at microwave frequencies.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A Distortion Compensating Flash Analog-to-Digital Conversion Technique.
IEEE J. Solid State Circuits, 2006

System Aspects of Analog to Digital Converter Designs.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Transmission line based FIR structures for high speed adaptive equalization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Rapid Simulation of Current Steering Digital-to-Analog Converters using Verilog-A.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A Technique for Accurate Frequency Response Measurement of Integrated Continuous-Time Filters.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Analysis of traveling wave and transversal analog adaptive equalizers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Continuous-time integrated FIR filters at microwave frequencies.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

A fixed transconductance bias technique for CMOS analog integrated circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2001
A 165 MS/s 8-bit CMOS A/D converter with background offset cancellation.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
Widely programmable high-frequency continuous-time filters in digital CMOS technology.
IEEE J. Solid State Circuits, 2000

A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process.
IEEE J. Solid State Circuits, 2000

1999
Modeling of accumulation MOS capacitors for analog design in digital VLSI processes.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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