Sascha Mühlbach
According to our database1,
Sascha Mühlbach
authored at least 15 papers
between 2007 and 2015.
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Bibliography
2015
Reconfigurable architectures and design automation tools for application-level network security.
PhD thesis, 2015
2014
A Reconfigurable Platform and Programming Tools for High-Level Network Applications Demonstrated as a Hardware Honeypot.
IEEE J. Sel. Areas Commun., 2014
Rekonfigurierbare Architekturen und Entwurfswerkzeuge für anwendungsspezifische Hardware im Bereich der Netzwerksicherheit.
Proceedings of the Ausgezeichnete Informatikdissertationen 2014, 2014
2012
NetStage/DPR: A self-reconfiguring platform for active and passive network security operations.
Microprocess. Microsystems, 2012
A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection.
Int. J. Reconfigurable Comput., 2012
Malacoda: towards high-level compilation of network security applications on reconfigurable hardware.
Proceedings of the Symposium on Architecture for Networking and Communications Systems, 2012
2011
A novel network platform for secure and efficient malware collection based on reconfigurable hardware logic.
Proceedings of the 2011 World Congress on Internet Security, 2011
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
2010
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
An FPGA-based scalable platform for high-speed malware collection in large IP networks.
Proceedings of the International Conference on Field-Programmable Technology, 2010
MalCoBox: Designing a 10 Gb/s Malware Collection Honeypot Using Reconfigurable Technology.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
Side-Channel Resistance Evaluation of a Neural Network Based Lightweight Cryptography Scheme.
Proceedings of the IEEE/IFIP 8th International Conference on Embedded and Ubiquitous Computing, 2010
2008
J. Syst. Archit., 2008
2007
Secure and Authenticated Communication in Chip-Level Microcomputer Bus Systems with Tree Parity Machines.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007