Satendra Kumar Maurya

According to our database1, Satendra Kumar Maurya authored at least 6 papers between 2009 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2013
Low Complexity Out-of-Order Issue Logic Using Static Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2013

2011
A Dynamic Longest Prefix Matching Content Addressable Memory for IP Routing.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Specialized Static Content Addressable Memory for Longest Prefix Matching in Internet Protocol Routing.
J. Low Power Electron., 2011

2010
Fast and scalable priority encoding using static CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Out-of-order issue logic using sorting networks.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
Low power fast and dense longest prefix match content addressable memory for IP routers.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009


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