Lawrence T. Clark

According to our database1, Lawrence T. Clark authored at least 62 papers between 1990 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Physically Unclonable Functions Using Foundry SRAM Cells.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Itemization and Track Limitations of Fan-Out-Free Functions for Static CMOS Functional Cells.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Reliable techniques for integrated circuit identification and true random number generation using 1.5-transistor flash memory.
Integr., 2019

2018
SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2017
Design flows and collateral for the ASAP7 7nm FinFET predictive process design kit.
Proceedings of the 2017 IEEE International Conference on Microelectronic Systems Education, 2017

Design technology co-optimization of back end of line design rules for a 7 nm predictive process design kit.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Integrated circuit identification and true random numbers using 1.5-transistor flash memory.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Robust 7-nm SRAM design on a predictive PDK.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

ASAP7 predictive design kit development and cell design technology co-optimization: Invited paper.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Design with sub-10 nm FinFET technologies.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
SRAM-Based Unique Chip Identifier Techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2016

An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits.
IEEE Trans. Computers, 2016

ASAP7: A 7-nm finFET predictive process design kit.
Microelectron. J., 2016

2015
Guest Editorial: Special Section on the 2014 IEEE Custom Integrated Circuits Conference (CICC 2014).
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Advanced encryption system with dynamic pipeline reconfiguration for minimum energy operation.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Delay and power tradeoffs for static and dynamic register files.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Simple and accurate single event charge collection macro modeling for circuit simulation.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Temporal pulse-clocked multi-bit flip-flop mitigating SET and SEU.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A soft-error hardened process portable embedded microprocessor.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Methodical Design Approaches to Radiation Effects Analysis and Mitigation in Flip-Flop Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Methodology to optimize critical node separation in hardened flip-flops.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Transient response exploration of SRAM cell metastable states caused by ionizing radiation with 3D mixed mode simulation.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Independent N and P process monitors for body bias based process corner correction.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Low Complexity Out-of-Order Issue Logic Using Static Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Reducing Transistor Variability for High Performance Low Power Chips.
IEEE Micro, 2013

SRAM cell optimization for low AVT transistors.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2011
A Dynamic Longest Prefix Matching Content Addressable Memory for IP Routing.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Specialized Static Content Addressable Memory for Longest Prefix Matching in Internet Protocol Routing.
J. Low Power Electron., 2011

Validation of and delay variation in total ionizing dose hardened standard cell libraries.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Efficient voltage conversion for SRAM low standby power modes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Improved circuits for microchip identification using SRAM mismatch.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Fast and scalable priority encoding using static CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Fast low power translation lookaside buffers using hierarchical NAND match lines.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Out-of-order issue logic using sorting networks.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

In-situ characterization and extraction of SRAM variability.
Proceedings of the 47th Design Automation Conference, 2010

Single event transient mitigation in cache memory using transient error checking circuits.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Low-Power Race-Free Programmable Logic Arrays.
IEEE J. Solid State Circuits, 2009

Introduction to the Special Issue on the 2008 IEEE Custom Integrated Circuits Conference.
IEEE J. Solid State Circuits, 2009

Reducing process variation impact on replica-timed static random access memory sense timing.
Integr., 2009

Low power fast and dense longest prefix match content addressable memory for IP routers.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008
Low-Power Dynamic Memory Word Line Decoding for Static Random Access Memories.
IEEE J. Solid State Circuits, 2008

Introduction to the Special Issue on the IEEE 2007 Custom Integrated Circuits Conference.
IEEE J. Solid State Circuits, 2008

Leakage Controlled Read Stable Static Random Access Memories.
J. Comput., 2008

High performance set associative translation lookaside buffers for low power microprocessors.
Integr., 2008

Critical race-free low-power nand match line content addressable memory tagged cache memory.
IET Comput. Digit. Tech., 2008

Amorphous silicon logic circuits on flexible substrates.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

LCSRAM: A Leakage Controlled Six-transistor Static Random Access Memory Cell with Intrinsically High Read Stability.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Low Standby Power Flip-flop with Reduced Circuit and Control Complexity.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Six and Seven Transistor Leakage Suppressed SRAM Cells with Improved Read Stability.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Low-power high-performance nand match line content addressable memories.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Subthreshold to Above Threshold Level Shifter Design.
J. Low Power Electron., 2006

Static Random Access Memory Cells with Intrinsically High Read Stability and Low Standby Power.
J. Low Power Electron., 2006

Circuit architecture for low-power race-free programmable logic arrays.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

A 0.13 μm Low-power Race-free Programmable Logic Array.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Robust Design of High Fan-In/Out Subthreshold Circuits.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Reducing power in flexible a-Si digital circuits while preserving state.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Managing standby and active mode leakage power in deep sub-micron design.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003
Reducing translation lookaside buffer active power.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2002
Standby power management for a 0.18µm microprocessor.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

1990
VLSI Implementation of Neural Classifiers.
Neural Comput., 1990


  Loading...