Saurabh Chaudhury
Orcid: 0000-0001-8116-1903
According to our database1,
Saurabh Chaudhury
authored at least 21 papers
between 2006 and 2023.
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Bibliography
2023
2022
Gray level size zone matrix for rice grain classification using back propagation neural network: a comparative study.
Int. J. Syst. Assur. Eng. Manag., 2022
2021
Fast and High-Performing 1-Bit Full Adder Circuit Based on Input Switching Activity Patterns and Gate Diffusion Input Technique.
Circuits Syst. Signal Process., 2021
2020
Modified Moth-Flame Optimization Algorithm-Based Multilevel Minimum Cross Entropy Thresholding for Image Segmentation.
Int. J. Swarm Intell. Res., 2020
Comparative analysis of texture feature extraction techniques for rice grain classification.
IET Image Process., 2020
IET Circuits Devices Syst., 2020
2019
Multim. Tools Appl., 2019
Brain MR Image Multilevel Thresholding by Using Particle Swarm Optimization, Otsu Method and Anisotropic Diffusion.
Int. J. Appl. Metaheuristic Comput., 2019
IET Circuits Devices Syst., 2019
2017
A Novel SRAM Cell Design with a Body-Bias Controller Circuit for Low Leakage, High Speed and Improved Stability.
Wirel. Pers. Commun., 2017
Moth-Flame Optimization Algorithm Based Multilevel Thresholding for Image Segmentation.
Int. J. Appl. Metaheuristic Comput., 2017
Expert Syst. Appl., 2017
Dynamic Threshold Sleep Transistor Technique for High Speed and Low Leakage in CMOS Circuits.
Circuits Syst. Signal Process., 2017
2016
J. Circuits Syst. Comput., 2016
Efficient technique for rice grain classification using back-propagation neural network and wavelet decomposition.
IET Comput. Vis., 2016
2014
An Integrated Approach of Logarithmic Transformation and Histogram Equalization for Image Enhancement.
Proceedings of Fourth International Conference on Soft Computing for Problem Solving, 2014
2011
Algorithmic Optimization of BDDs and Performance Evaluation for Multi-level Logic Circuits with Area and Power Trade-offs.
Circuits Syst., 2011
2010
Genetic algorithm based variable ordering of BDDs for multi-level logic optimization with area-power trade-offs.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009
State Assignment and Polarity Selection for Low Dynamic Power and Testable Finite State Machine Synthesis.
J. Low Power Electron., 2009
2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006