Sebastian Cieslak

According to our database1, Sebastian Cieslak authored at least 2 papers in 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Design and Verification Environment for RISC-V Processor Cores.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

Retargeting the MIPS-II CPU Core to the RISC-V Architecture.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019


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