SeongHwan Cho
Orcid: 0000-0001-7938-2694
According to our database1,
SeongHwan Cho
authored at least 93 papers
between 2002 and 2024.
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Bibliography
2024
3.1 A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/°C from -20°C to 125°C.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
19.1 A 7.5GHz Subharmonic Injection-Locked Clock Multiplier with a 62.5MHz Reference, -259.7dB FoMJ, and -56.6dBc Reference Spur.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
An Adaptive Filter Based Motion Artifact Cancellation Technique Using Multi-Wavelength PPG for Accurate HR Estimation.
IEEE Trans. Biomed. Circuits Syst., October, 2023
Introduction to the Special Section on the 2022 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits, October, 2023
An Output-Capacitorless Analog LDO Featuring Frequency Compensation of Four-Stage Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
A 43.3-μW Biopotential Amplifier With Tolerance to Common-Mode Interference of 18 V<sub>pp</sub> and T-CMRR of 105 dB in 180-nm CMOS.
IEEE J. Solid State Circuits, February, 2023
A 3.68 aF<sub>rms</sub> Resolution Continuous-Time Bandpass Δ Σ Capacitance-to-Digital Converter for Full-CMOS Sensors in 0.18 μm CMOS.
IEEE J. Solid State Circuits, 2023
IEEE J. Solid State Circuits, 2023
A 1, 024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A Jitter-Programmable Bang-Bang Phase-Locked Loop Using PVT Invariant Stochastic Jitter Monitor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A 43 nW, 32 kHz, ±4.2 ppm Piecewise Linear Temperature-Compensated Crystal Oscillator With ΔΣ-Modulated Load Capacitance.
IEEE J. Solid State Circuits, 2022
IEICE Electron. Express, 2022
A Comprehensive Analysis of Today's Malware and Its Distribution Network: Common Adversary Strategies and Implications.
IEEE Access, 2022
A 2.54μJ∙ppm<sup>2</sup>-FOMS Supply- and Temperature-Independent Time-Locked ΔΣ Capacitance-to-Digital Converter in 0.18-μm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
A 24.8-μW Biopotential Amplifier Tolerant to 15-V<sub>PP</sub> Common-Mode Interference for Two-Electrode ECG Recording in 180-nm CMOS.
IEEE J. Solid State Circuits, 2021
IEEE J. Solid State Circuits, 2021
A 3.68aFrms Resolution 183dB FoMs 4<sup>th</sup>-order Continuous-Time Bandpass ∆Σ Capacitance-to-Digital Converter in 0.18µm CMOS.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
An Energy-Efficient Voltage Step-up System for 3D NAND Flash using Charge-Compensating Regulator.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
28.6 A 22.6µ W Biopotential Amplifier with Adaptive Common-Mode Interference Cancelation Achieving Total-CMRR of 104dB and CMI Tolerance of 15Vpp in 0.18µm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
An Offset Charge Compensating Biphasic Neuro - stimulation for Faradaic DC-Current Reduction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
An Adaptive Clocking System using Supply Tracking Clock Modulator with Background Calibrated Supply-Sensitivity in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A Capacitance-to-Digital Converter with Differential Bondwire Accelerometer, On-chip Air Pressure and Humidity Sensor in 0.18 μm CMOS.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
A Second-Order ΔΣ Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
An On-Chip Thermal Monitoring System With a Temperature Sensing Area of 52 µm<sup>2</sup> in 180-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 2.92-µW Capacitance-to-Digital Converter With Differential Bondwire Accelerometer, On-Chip Air Pressure, and Humidity Sensor in 0.18-µm CMOS.
IEEE J. Solid State Circuits, 2019
A 27.8μW Biopotential Amplifier Tolerant to 30Vpp Common-Mode Interference for Two-Electrode ECG Recording in 0.18μm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A Low-Power Piezoelectric Speaker Driver Using LC Oscillator for Acoustic Communication.
Proceedings of the 2019 International SoC Design Conference, 2019
An On-Off Keying LC Oscillator-Based Acoustic Transmitter with Fast Turn-On and Turn-Off Time.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Biomed. Circuits Syst., 2018
An Ultra-High Input Impedance Analog Front End Using Self-Calibrated Positive Feedback.
IEEE J. Solid State Circuits, 2018
A 2.69UW Dual Quantization-Based Capacitance-to-Digital Converter for Pressure, Humidity, and Acceleration Sensing in 0.18UM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
A 2.3-mW 0.01-mm<sup>2</sup> 1.25-GHz Quadrature Signal Corrector With 1.1-ps Error for Mobile DRAM Interface in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique.
IEEE J. Solid State Circuits, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
A 0.22 ps rms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter.
IEEE J. Solid State Circuits, 2015
Integrated All Electrical Pulse Wave Velocity and Respiration Sensors Using Bio-Impedance.
IEEE J. Solid State Circuits, 2015
5.10 A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
A 148fs<sub>rms</sub> Integrated Noise 4 MHz Bandwidth Second-Order ΔΣ Time-to-Digital Converter With Gated Switched-Ring Oscillator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register.
IEEE J. Solid State Circuits, 2014
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier.
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillator.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
A Highly-Digital VCO-Based Analog-to-Digital Converter Using Phase Interpolator and Digital Calibration.
IEEE Trans. Very Large Scale Integr. Syst., 2012
A 2.5-Gb/s On-Chip Interconnect Transceiver With Crosstalk and ISI Equalizer in 130 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL.
IEEE J. Solid State Circuits, 2012
A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 μ m CMOS.
IEEE J. Solid State Circuits, 2012
A 1.4-µW 24.9-ppm/°C Current Reference With Process-Insensitive Temperature Compensation in 0.18-µm CMOS.
IEEE J. Solid State Circuits, 2012
A High-Frequency Compensated Crosstalk and ISI Equalizer for Multi-Channel On-Chip Interconnect in 130-nm CMOS.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier.
Proceedings of the Symposium on VLSI Circuits, 2012
An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Session 19 overview: 20+ Gb/s wireline transceivers and injection-locked clocking: Wireline subcommittee.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
A 470-µW 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider With an In-Phase Dual-Input Injection Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2011
A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A fractional-N frequency synthesizer using high-OSR delta-sigma modulator and nested-PLL.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder.
IEICE Trans. Electron., 2010
A background KDCO compensation technique for constant bandwidth in all-digital phase-locked loop.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A 2.4-GHz reference doubled fractional-N PLL with dual phase detector in 0.13-μm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A 10-bit 300MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
CMRR enhancement technique for IA using three IAs for bio-medical sensor applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
Introduction to the Special Section on the 2008 Asian Solid-State Circuits Conference (A-SSCC'08).
IEEE J. Solid State Circuits, 2009
IEICE Trans. Electron., 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
A Bio-impedance Measurement System for Portable Monitoring of Heart Rate and Pulse Wave Velocity using Small Body Area.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
An ultra low power UHF RFID tag front-end for EPCglobal Gen2 with novel clock-free decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
2006
Proceedings of the IEEE 17th International Symposium on Personal, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of IEEE International Conference on Communications, 2005
2004
IEEE J. Solid State Circuits, 2004
2003
IEEE Trans. Circuits Syst. II Express Briefs, 2003
2002
PhD thesis, 2002