Seoungju Chung

According to our database, Seoungju Chung authored at least 2 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

First Demonstration of Fully Integrated 16 nm Half-Pitch Selector Only Memory (SOM) for Emerging CXL Memory.

Myoungsub Kim, Yooncheol Bae, Jaehyuk Park, Jeongho Yeon, Hyungjoon Shim, Sehyun Jin, Hyunsoo Kim, Sangchul Oh, Gapsok Do, Dongyeol Yun, Hyung Dong Lee, David Ahn, Junghun Lee, Muhui Park, Junghyuk Yoon, Jeongho Yi, Taekseung Kim, Gain Park, Seoungju Chung, Junho Cheon, Sujin Chae, Namkyun Park, Kyunghoon Kim, Dongyean Oh, Jaeyun Yi, Seonyong Cha

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2017

23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture.

Kwangmyoung Rho, Kenji Tsuchida, Dongkeun Kim, Yutaka Shirai, Jihyae Bae, Tsuneo Inaba, Hiromi Noro, Hyunin Moon, Sungwoong Chung, Kazumasa Sunouchi, Jinwon Park, Kiseon Park, Akihito Yamamoto, Seoungju Chung, Hyeongon Kim, Hisato Oyamatsu, Jonghoon Oh

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017