Seungjae Moon

Orcid: 0009-0002-5924-7000

According to our database1, Seungjae Moon authored at least 13 papers between 2022 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Adelia: A 4-nm LLM Processing Unit With Streamlined Dataflow and Dual-Mode Parallelism for Maximizing Hardware Efficiency.
IEEE J. Solid State Circuits, April, 2026

OV-Stitcher: A Global Context-Aware Framework for Training-Free Open-Vocabulary Semantic Segmentation.
CoRR, April, 2026

RecycleLoRA: Rank-Revealing QR-Based Dual-LoRA Subspace Adaptation for Domain Generalized Semantic Segmentation.
CoRR, March, 2026

2025
Hybe: GPU-NPU Hybrid System for Efficient LLM Inference with Million-Token Context Window.
Proceedings of the 52nd Annual International Symposium on Computer Architecture, 2025

Adelia: A 4nm LLM Processor for Efficient Generative Al Inference.
Proceedings of the IEEE Hot Chips 37 Symposium, 2025

2024
A Latency Processing Unit: A Latency-Optimized and Highly Scalable Processor for Large Language Model Inference.
IEEE Micro, 2024

LPU: A Latency-Optimized and Highly Scalable Processor for Large Language Model Inference.
CoRR, 2024

BLESS: Bandwidth and Locality Enhanced SMEM Seeding Acceleration for DNA Sequencing.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

Internal Compensation X-Ray Detector Pixel Circuit with IGZO TFT and Perovskite Single Crystal.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024

Micro LED Pixel Circuit with Threshold Voltage Compensation.
Proceedings of the International Conference on Electronics, Information, and Communication, 2024

2023
HyperAccel Latency Processing Unit (LPU<sup>TM</sup>) Accelerating Hyperscale Models for Generative AI.
Proceedings of the 35th IEEE Hot Chips Symposium, 2023

2022
Exploration of Systolic-Vector Architecture with Resource Scheduling for Dynamic ML Workloads.
CoRR, 2022

DFX: A Low-latency Multi-FPGA Appliance for Accelerating Transformer-based Text Generation.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022


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