Seyed Alireza Zahrai

According to our database1, Seyed Alireza Zahrai authored at least 8 papers between 2015 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2019
Comparator Design and Calibration for Flash ADCs within Two-Step ADC Architectures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Design Considerations and Experimental Verification of a 10.5mW 1GS/s Hybrid ADC for Portable Wireless Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A Low-Power High-Speed Hybrid ADC With Merged Sample-and-Hold and DAC Functions for Efficient Subranging Time-Interleaved Operation.
IEEE Trans. Very Large Scale Integr. Syst., 2017

An Analog Front-End Chip With Self-Calibrated Input Impedance for Monitoring of Biosignals via Dry Electrode-Skin Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Design of clock generation circuitry for high-speed subranging time-interleaved ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2015
Digitally programmable offset compensation of comparators in flash ADCs for hybrid ADC architectures.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

On-chip digital calibration for automatic input impedance boosting during biopotential measurements.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A low-power hybrid ADC architecture for high-speed medium-resolution applications.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015


  Loading...