Shabbir Majeed Chaudhry

According to our database, Shabbir Majeed Chaudhry authored at least 4 papers between 2016 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

Design of an Improved Low-Power and High-Speed Booth Multiplier.

Ahsan Rafiq, Shabbir Majeed Chaudhry

Circuits Syst. Signal Process., 2021

2019

Design of a Feedback Loop Circuit for Quadrature Error Correction in 90-nm CMOS.

Muhammad Haseeb, Muhammad Usman, Shabbir Majeed Chaudhry

Proceedings of the International Conference on Frontiers of Information Technology, 2019

2018

A 15-Bit 85 MS/s Hybrid Flash-SAR ADC in 90-nm CMOS.

Anas Razzaq Ghumman, Shabbir Majeed Chaudhry

Circuits Syst. Signal Process., 2018

2016

A Reduced-sp- \(\hbox {D3L}_{\mathrm{sum}}\) Adder-Based High Frequency \(4\times 4\) Bit Multiplier Using Dadda Algorithm.

Zain Shabbir, Anas Razzaq Ghumman, Shabbir Majeed Chaudhry

Circuits Syst. Signal Process., 2016