Shadi M. Harb

Orcid: 0000-0001-8146-2837

According to our database1, Shadi M. Harb authored at least 14 papers between 2006 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
A novel self-timing CMOS first-edge take-all circuit for on-chip communication systems.
IET Comput. Digit. Tech., 2023

2021
Signal Integrity in High Speed 3D IC Design- A Case Study.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021

2017
A study of characterizing crosstalk effects in 3-D vias.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

2016
Oscillation ring testing methodology of TSVs in 3D stacked ICs.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

2015
Development, Implementation, Assessment of a Web-based Circuit Solver for Teaching Basic Electrical Circuits Theory.
Int. J. Online Eng., 2015

A CMOS High Resolution Multi-Edge Delay Generator.
Proceedings of the Nordic Circuits and Systems Conference, 2015

2011
A Shadow Dynamic Finite State Machine for Branch Prediction: An Alternative for the 2-bit Saturating Counter.
Informatica (Slovenia), 2011

A sub-1V CMOS voltage reference generator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2009
High speed I/O and thermal effect characterization of 3D stacked ICs.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Analytical Study of the Expected Number of Hops in Wireless Ad Hoc Network.
Proceedings of the Wireless Algorithms, 2008

High speed digital CMOS divide-by-N fequency divider.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
A low-power CAM using a 12-transistor design cell.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2006
A VLSI High-Performance Priority Encoder Using Standard CMOS Library.
IEEE Trans. Circuits Syst. II Express Briefs, 2006


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