Shahriar Shahramian

Orcid: 0000-0003-4295-9087

According to our database1, Shahriar Shahramian authored at least 15 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2023
Practical Approaches to Industrializing Near-THz Communication Systems.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2023

2022
Fully Integrated 2D Scalable TX/RX Chipset for D-Band Phased-Array-on-Glass Modules.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
Guest Editorial Introduction to the Special Section on the 2020 IEEE BCICTS Conference.
IEEE J. Solid State Circuits, 2021

2019
A Fully Integrated 384-Element, 16-Tile, $W$ -Band Phased Array With Self-Alignment and Self-Test.
IEEE J. Solid State Circuits, 2019

Introduction to the Special Section on the 2018 IEEE BCICTS Conference.
IEEE J. Solid State Circuits, 2019

2018
Introduction to the Special Section on the 2017 IEEE BCTM and IEEE CSICS Conferences.
IEEE J. Solid State Circuits, 2018

A fully integrated scalable W-band phased-array module with integrated antennas, self-alignment and self-test.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2016
Introduction to the Special Section on the 2015 Compound Semiconductor Integrated Circuit Symposium.
IEEE J. Solid State Circuits, 2016

2015
Demonstration of 112-Gbit/s optical transmission using 56GBaud PAM-4 driver and clock-and-data recovery ICs.
Proceedings of the European Conference on Optical Communication, 2015

2013
A 70-100 GHz Direct-Conversion Transmitter and Receiver Phased Array Chipset Demonstrating 10 Gb/s Wireless Link.
IEEE J. Solid State Circuits, 2013

2011
Design of a Dual W- and D-Band PLL.
IEEE J. Solid State Circuits, 2011

2009
A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees.
IEEE J. Solid State Circuits, 2009

2006
Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-$muhbox m$SiGe BiCMOS Technology.
IEEE J. Solid State Circuits, 2006

A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2004
Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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