Anthony Chan Carusone
Orcid: 0000-0002-0977-7516
According to our database1,
Anthony Chan Carusone
authored at least 113 papers
between 1999 and 2023.
Collaborative distances:
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Bibliography
2023
A 112-Gb/s - 8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes.
IEEE J. Solid State Circuits, March, 2023
A 32 Gb/s, 0.42 pJ/bit Passive Hybrid Simultaneous Bidirectional Transceiver for Die-to-Die Links.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Design and Optimization of Low-Dropout Voltage Regulator Using Relational Graph Neural Network and Reinforcement Learning in Open-Source SKY130 Process.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Reconfigurable 5-Channel Ring-Oscillator-Based TDC for Direct Time-of-Flight 3D Imaging.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Optimization of Quantized Analog Signal Processing Using Genetic Algorithms and μ-Law.
IEEE Open J. Circuits Syst., 2022
IEEE Open J. Circuits Syst., 2022
Estimation of Broadband Time-Interleaved ADC's Impairments and Performance Using Only Single-Tone Measurements.
IEEE Access, 2022
IEEE Access, 2022
Design Considerations for Time-Modulated Injection-Locked Phase Interpolators and Rotators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A 112 Gb/s -8.2 dBm Sensitivity 4-PAM Linear TIA in 16nm CMOS with Co-Packaged Photodiodes.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Open J. Circuits Syst., 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2020
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
IEEE J. Solid State Circuits, 2019
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
A Low-Power Pipelined-SAR ADC Using Boosted Bucket-Brigade Device for Residue Charge Processing.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A Sub-mW Integrating Mixer SAR Spectrum Sensor for Portable Cognitive Radio Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers.
IEEE J. Solid State Circuits, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
A sub-mW spectrum sensing architecture for portable IEEE 802.22 cognitive radio applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
IEEE J. Solid State Circuits, 2016
IEEE J. Solid State Circuits, 2016
A 20 Gb/s CMOS Optical Receiver With Limited-Bandwidth Front End and Local Feedback IIR-DFE.
IEEE J. Solid State Circuits, 2016
23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
Correction to "A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS".
IEEE J. Solid State Circuits, 2015
IEEE J. Solid State Circuits, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
Multi-phase bang-bang digital phase lock loop with accelerated frequency acquisition.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the ESSCIRC 2014, 2014
Proceedings of the ESSCIRC 2014, 2014
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
IEEE J. Solid State Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
IEEE J. Solid State Circuits, 2011
CMOS Technology Scaling Considerations for Multi-Gbps Optical Receivers With Integrated Photodetectors.
IEEE J. Solid State Circuits, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
A 5-Gbit/s CMOS Optical Receiver With Integrated Spatially Modulated Light Detector and Equalization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE J. Solid State Circuits, 2010
A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Progress and trends in multi-Gbps optical receivers with CMOS integrated photodetectors.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
A 32/16-Gb/s Dual-Mode Pulsewidth Modulation Pre-Emphasis (PWM-PE) Transmitter With 30-dB Loss Compensation Using a High-Speed CML Design Methodology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE J. Solid State Circuits, 2009
IEEE J. Solid State Circuits, 2009
Introduction to the Special Issue on the 2008 IEEE Custom Integrated Circuits Conference.
IEEE J. Solid State Circuits, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
A Delta-Sigma Modulator With a Widely Programmable Center Frequency and 82-dB Peak SNDR.
IEEE J. Solid State Circuits, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
A 32/16 Gb/s 4/2-PAM transmitter with PWM pre-Emphasis and 1.2 Vpp per side output swing in 0.13-μm CMOS.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-$muhbox m$SiGe BiCMOS Technology.
IEEE J. Solid State Circuits, 2006
A 3-Tap FIR Filter With Cascaded Distributed Tap Amplifiers for Equalization Up to 40 Gb/s in 0.18-$mu$m CMOS.
IEEE J. Solid State Circuits, 2006
A CMOS finite impulse response filter with a crossover traveling wave topology for equalization up to 30 Gb/s.
IEEE J. Solid State Circuits, 2006
A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-$muhbox m$SiGe BiCMOS Technology.
IEEE J. Solid State Circuits, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
A comparison of equalizers for compensating polarization-mode dispersion in 40-Gb/s optical systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
IEEE Trans. Circuits Syst. II Express Briefs, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
A 5th order Gm-C filter in 0.25 µm CMOS with digitally programmable poles and zeroes.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999