Anthony Chan Carusone

According to our database1, Anthony Chan Carusone authored at least 91 papers between 1999 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2020

An Adaptive Spatial Blocker Cancellation Receiver for Multiple Antenna Systems.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

Discrete Multitone Signalling for Wireline Communication.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

All-Digital Calibration Algorithms to Correct for Static Non-Linearities in ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
A 64-Gb/s 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET.
IEEE J. Solid State Circuits, 2019

A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

TDC Sharing in SPAD-Based Direct Time-of-Flight 3D Imaging Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
A Low-Power Pipelined-SAR ADC Using Boosted Bucket-Brigade Device for Residue Charge Processing.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Nano-Watt MOS-Only Voltage Reference With High-Slope PTAT Voltage Generators.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A Sub-mW Integrating Mixer SAR Spectrum Sensor for Portable Cognitive Radio Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers.
IEEE J. Solid State Circuits, 2018

A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Direct Time-of-Flight TCSPC Analytical Modeling Including Dead-Time Effects.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Filtering ADCs for wireless receivers: A survey.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A sub-mW spectrum sensing architecture for portable IEEE 802.22 cognitive radio applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Low-power CMOS receivers for short reach optical communication.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 40-Gbps 0.5-pJ/bit VCSEL driver in 28nm CMOS with complex zero equalizer.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5~µs.
IEEE J. Solid State Circuits, 2016

Capacitively-Coupled CMOS VCSEL Driver Circuits.
IEEE J. Solid State Circuits, 2016

A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication.
IEEE J. Solid State Circuits, 2016

A 20 Gb/s CMOS Optical Receiver With Limited-Bandwidth Front End and Local Feedback IIR-DFE.
IEEE J. Solid State Circuits, 2016

23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
Correction to "A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS".
IEEE J. Solid State Circuits, 2015

A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS.
IEEE J. Solid State Circuits, 2015

A 19.6-Gbps CMOS optical receiver with local feedback IIR DFE.
Proceedings of the Symposium on VLSI Circuits, 2015

A 26-Gb/s 1.80-pJ/b CMOS-driven transmitter for 850-nm common-cathode VCSELs.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2015

Cycle-slipping pull-in range of bang-bang PLLs.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Multi-phase bang-bang digital phase lock loop with accelerated frequency acquisition.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 20 Gb/s 0.3 pJ/b single-ended die-to-die transceiver in 28 nm-SOI CMOS.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Time interleaved C-2C SAR ADC with background timing skew calibration in 65nm CMOS.
Proceedings of the ESSCIRC 2014, 2014

A 10Gb/s 4.1mW 2-IIR + 1-discrete-tap DFE in 28nm-LP CMOS.
Proceedings of the ESSCIRC 2014, 2014

2013
Modeling Oscillator Injection Locking Using the Phase Domain Response.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC.
IEEE J. Solid State Circuits, 2013

F5: Frequency generation and clock distribution.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Channel characterization using jitter measurements.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 1-1-1-1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs.
IEEE J. Solid State Circuits, 2012

10-40 Gb/s I/O design for data communications.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A dead-zone free and linearized digital PLL.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Design of a Dual W- and D-Band PLL.
IEEE J. Solid State Circuits, 2011

7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS.
IEEE J. Solid State Circuits, 2011

CMOS Technology Scaling Considerations for Multi-Gbps Optical Receivers With Integrated Photodetectors.
IEEE J. Solid State Circuits, 2011

A 1-1-1-1 MASH delta-sigma modulator using dynamic comparator-based OTAs.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A 5-Gbit/s CMOS Optical Receiver With Integrated Spatially Modulated Light Detector and Equalization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Multi-Gb/s Bit-by-Bit Receiver Architectures for 1-D Partial-Response Channels.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

5-10 Gb/s 70 mW Burst Mode AC Coupled Receiver in 90-nm CMOS.
IEEE J. Solid State Circuits, 2010

A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 15-Gb/s preamplifier with 10-dB gain control and 8-mV sensitivity in 65-nm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Progress and trends in multi-Gbps optical receivers with CMOS integrated photodetectors.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Introducing Jump-Start Tutorials.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Guest Editorial Special Issue on ISCAS 2008.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A 32/16-Gb/s Dual-Mode Pulsewidth Modulation Pre-Emphasis (PWM-PE) Transmitter With 30-dB Loss Compensation Using a High-Speed CML Design Methodology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees.
IEEE J. Solid State Circuits, 2009

CMOS Oscillators for Clock Distribution and Injection-Locked Deskew.
IEEE J. Solid State Circuits, 2009

Introduction to the Special Issue on the 2008 IEEE Custom Integrated Circuits Conference.
IEEE J. Solid State Circuits, 2009

An Anti-aliasing Multi-rate SigmaDelta Modulator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A Time-Interleaved DeltaSigma-DAC Architecture Clocked at the Nyquist Rate.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

A Delta-Sigma Modulator With a Widely Programmable Center Frequency and 82-dB Peak SNDR.
IEEE J. Solid State Circuits, 2008

Power Reduction Techniques for LDPC Decoders.
IEEE J. Solid State Circuits, 2008

A passive filter aided timing recovery scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

High-performance chip-to-chip signaling.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

20 GHz low power QVCO and De-skew techniques in 0.13μm digital CMOS.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A 32/16 Gb/s 4/2-PAM transmitter with PWM pre-Emphasis and 1.2 Vpp per side output swing in 0.13-μm CMOS.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Editorial ISCAS 2006 Special Section on Analog Circuits and Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Modeling and Design of Multilevel Bang-Bang CDRs in the Presence of ISI and Noise.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A Baud-Rate Timing Recovery Scheme With a Dual-Function Analog Filter.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

An Equalizer Adaptation Algorithm to Reduce Jitter in Binary Receivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

A bit-serial approximate min-sum LDPC decoder and FPGA implementation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A 19-GHz Broadband Amplifier Using a g<sub>m</sub>-Boosted Cascode in 0.18-μm CMOS.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A comparison of equalizers for compensating polarization-mode dispersion in 40-Gb/s optical systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Jitter equalization for binary baseband communication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 40 Gb/s transversal filter in 0.18 /spl mu/m CMOS using distributed amplifiers.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
Hardware reduction by combining pipelined A/D conversion and FIR filtering for channel equalization.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Clock recovery in high-speed multilevel serial links.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A sigma-delta based open-loop frequency modulator.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
A 5th order Gm-C filter in 0.25 µm CMOS with digitally programmable poles and zeroes.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Analog filter adaptation using a dithered linear search algorithm.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

1999
Obtaining digital gradient signals for analog adaptive filters.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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