Shao-Ku Kao

Jian-Jiun Chen

Chien-Hung Liao

IEEE Access, 2022

2019

A programmbale 8-channel multiphase clock generator with 360 phases for focus ultrasound applications.

[BibT_eX]

[DOI]

Shih-Hung Cheng

Microelectron. J., 2019

2018

A 13.56 MHz CMOS High-Efficiency Active Rectifier With Dynamically Controllable Comparator for Biomedical Wireless Power Transfer Systems.

[BibT_eX]

[DOI]

Cihun-Siyong Alex Gong

IEEE Access, 2018

2016

Output capacitor-free low-dropout regulator with fast transient response and ultra small compensation capacitor.

[BibT_eX]

[DOI]

Microelectron. J., 2016

An all-digital DLL with duty-cycle correction using reusable TDC.

[BibT_eX]

[DOI]

Yi-Hsien Hsieh

Int. J. Circuit Theory Appl., 2016

A self-calibrated delay-locked loop with low static phase error.

[BibT_eX]

[DOI]

Jian-Da Lin

Int. J. Circuit Theory Appl., 2016

2015

All-digital controlled boost DC-DC converter with all-digital DLL-based calibration.

[BibT_eX]

[DOI]

Jen-Hou Wu

Microelectron. J., 2015

Pulsewidth control loop with a frequency detector for wide frequency range operation.

[BibT_eX]

[DOI]

Yong-De You

Microelectron. J., 2015

A fast-corrected all-digital DCC with synchronous input clock.

[BibT_eX]

[DOI]

Sheng-Hung Hsueh

Int. J. Circuit Theory Appl., 2015

2014

A VCO-based phase-expanding conversion designed for time-domain data converters.

[BibT_eX]

[DOI]

Yi-Fu Tang

Microelectron. J., 2014

Frequency presetting and phase error detection technique for fast-locking phase-locked loop.

[BibT_eX]

[DOI]

Microelectron. J., 2014

2013

A delay-locked loop with self-calibration circuit for reducing phase error.

[BibT_eX]

[DOI]

Microelectron. J., 2013

2011

Clock buffer with duty cycle corrector.

[BibT_eX]

[DOI]

Yong-De You

Microelectron. J., 2011

2008

A Delay-Locked Loop With Statistical Background Calibration.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

2007

A 62.5-625-MHz Anti-Reset All-Digital Delay-Locked Loop.

[BibT_eX]

[DOI]

Bo-Jiun Chen

IEEE Trans. Circuits Syst. II Express Briefs, 2007

2006

All-Digital Fast-Locked Synchronous Duty-Cycle Corrector.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles.

[BibT_eX]

[DOI]

You-Jen Wang

IEEE J. Solid State Circuits, 2006

All-Digital Clock Deskew Buffer with Variable Duty Cycles.

[BibT_eX]

[DOI]