Shigetaka Kasuga

According to our database1, Shigetaka Kasuga authored at least 9 papers between 2004 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2022
A Nearly Interference-Free and Depth-Resolution-Configurable Time-of-Flight System Based on a Mega-Pixel Vertical Avalanche Photodiodes CMOS Image Sensor.
IEEE Open J. Circuits Syst., 2022

2020
5.2 A 1200×900 6µm 450fps Geiger-Mode Vertical Avalanche Photodiodes CMOS Image Sensor for a 250m Time-of-Flight Ranging System Using Direct-Indirect-Mixed Frame Synthesis with Configurable-Depth-Resolution Down to 10cm.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 400×400-Pixel 6μm-Pitch Vertical Avalanche Photodiodes CMOS Image Sensor Based on 150ps-Fast Capacitive Relaxation Quenching in Geiger Mode for Synthesis of Arbitrary Gain Images.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A 250 m Direct Time-of-Flight Ranging System Based on a Synthesis of Sub-Ranging Images and a Vertical Avalanche Photo-Diodes (VAPD) CMOS Image Sensor.
Sensors, 2018

A 220 M-Range Direct Time-of-Flight 688 × 384 CMOS Image Sensor with Sub-Photon Signal Extraction (SPSE) Pixels Using Vertical Avalanche Photo-Diodes and 6 KHz Light Pulse Counters.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2016
6.6 A 1280×720 single-photon-detecting image sensor with 100dB dynamic range using a sensitivity-boosting technique.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2010
A 2.2/3-inch 4K2K CMOS image sensor based on dual resolution and exposure technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008
A 140dB-Dynamic-Range MOS Image Sensor with In-Pixel Multiple-Exposure Synthesis.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2004
1/4-inch 2-mpixel MOS image sensor with 1.75 transistors/pixel.
IEEE J. Solid State Circuits, 2004


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