Shinji Sugatani

Orcid: 0000-0001-6062-5000

According to our database¹, Shinji Sugatani authored at least 3 papers between 2023 and 2025.

Collaborative distances:

Dijkstra number² of six.
Erdős number³ of five.

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2025

A Through Silicon Via (TSV) Architecture of the Bumpless Build Cube (BBCube) for Stacked Memory Devices.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2025

Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WOW and COW.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2025

2023

Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WoW and CoW to Provide TB/s Bandwidth with Lowest Bit Access Energy.

[BibT_eX]

[DOI]

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Shinji Sugatani

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