Koji Sakui

According to our database1, Koji Sakui authored at least 16 papers between 1994 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2012, "For the contribution to NAND flash memories".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WoW and CoW to Provide TB/s Bandwidth with Lowest Bit Access Energy.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022
Dynamic Flash Memory with Fast Block Refresh.
Proceedings of the 20th Non-Volatile Memory Technology Symposium, 2022

2021
Reliability of Wafer-Level Ultra-Thinning down to 3 µm using 20 nm-Node DRAMs.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT).
Proceedings of the IEEE International Memory Workshop, 2021

1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar.
Proceedings of the IEEE International Memory Workshop, 2021

2019
Three-dimensional Integration (3DI) with Bumpless Interconnects for Tera-scale Generation : High Speed, Low Power, and Ultra-small Operating Platform.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN) with the Bumpless TSV Technology.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2010
Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET.
IEICE Trans. Electron., 2010

Design of 30 nm FinFETs and Double Gate MOSFETs with Halo Structure.
IEICE Trans. Electron., 2010

A compact and low power logic design for multi-pillar vertical MOSFETs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2000
A source-line programming scheme for low-voltage operation NAND flash memories.
IEEE J. Solid State Circuits, 2000

1999
A negative V<sub>th</sub> cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories.
IEEE J. Solid State Circuits, 1999

A 130-mm/<sup>2</sup>, 256-Mbit NAND flash with shallow trench isolation technology.
IEEE J. Solid State Circuits, 1999

A CMOS bandgap reference circuit with sub-1-V operation.
IEEE J. Solid State Circuits, 1999

1997
A 120-mm<sup>2</sup> 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed.
IEEE J. Solid State Circuits, 1997

1994
A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory.
IEEE J. Solid State Circuits, November, 1994


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