Shirisha Gourishetty

According to our database, Shirisha Gourishetty authored at least 3 papers in 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization Algorithms.

Prateek Gupta, Harshini Mandadapu, Shirisha Gourishetty, Zia Abbas

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

PVT Variations Aware Robust Transistor Sizing for Power-Delay Optimal CMOS Digital Circuit Design.

Prateek Gupta, Shirisha Gourishetty, Harshini Mandadapu, Zia Abbas

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Highly Accurate Machine Learning Approach to Modelling PVT Variation Aware Leakage Power in FinFET Digital Circuits.

Shirisha Gourishetty, Harshini Mandadapu, Andleeb Zahra, Zia Abbas

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019