Shugang Wei
According to our database1,
Shugang Wei
authored at least 26 papers
between 1990 and 2020.
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Bibliography
2020
J. Circuits Syst. Comput., 2020
2016
Proceedings of the International SoC Design Conference, 2016
2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
2014
IEICE Electron. Express, 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
2013
High-Speed Modular Multipliers Based on a New Binary Signed-Digit Adder Tree Structure.
J. Circuits Syst. Comput., 2013
RESIDUE-WEIGHTED NUMBER CONVERSION FOR MODULI SET {2<sup>n</sup>-1, 2<sup>n</sup> + 1, 2<sup>2n</sup> + 1, 2<sup>n</sup>} USING SIGNED-DIGIT NUMBER.
J. Circuits Syst. Comput., 2013
2012
Residue-weighted number conversion for moduli set {22<sup>n</sup> - 1, 2<sup>2n+1</sup> - 1, 2<sup>n</sup>} using signed-digit number.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
An RSA encryption implementation method using residue signed-digit arithmetic circuits.
Proceedings of the 5th International Conference on BioMedical Engineering and Informatics, 2012
2011
Efficient residue checker using new binary modular adder tree structure for error detection of arithmetic.
Proceedings of the Eighth International Conference on Fuzzy Systems and Knowledge Discovery, 2011
2006
Modulo (2<sup>p</sup> plusminus 1) Multipliers Using a Three-operand Modular Signed-digit Addition Algorithm.
J. Circuits Syst. Comput., 2006
Weighted-to-residue and residue-to-weighted converters with three-moduli (2<sup>n</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>+1) signed-digit architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Dynamic Range Compression Characteristics Using an Interpolating Polynomial for Digital Audio Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Number conversions between RNS and mixed-radix number system based on Modulo (2<sup>p - 1</sup>) signed-digit arithmetic.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
2003
Residue Checker with Signed-Digit Arithmetic for Error Detection of Arithmetic Circuits.
J. Circuits Syst. Comput., 2003
Modulo (2<sup>p</sup> ± 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
Residue signed-digit arithmetic circuit with a complement of modulus and the application to RSA encryption processor.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Fast modular multiplication using Booth recoding based on signed-digit number arithmetic.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Residue Arithmetic Multiplier Based on the Radix-4 Signed-Digit Multiple-Valued Arithmetic Circuits.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
1998
Residue Arithmetic Circuits Based on the Signed-Digit Multiple-Valued Arithmetic Circuits.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
1991
Syst. Comput. Jpn., 1991
1990
Design of an RSA Encryption Processor Based on Signed-Digit Multivalued Arithmetic Circuits.
Syst. Comput. Jpn., 1990