Michitaka Kameyama

According to our database1, Michitaka Kameyama authored at least 204 papers between 1977 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1997, "For contributions to the development of multiple-valued intelligent integrated systems.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
Optimization of LNN Reversible Circuits Using an Analytic Sifting Method.
J. Circuits Syst. Comput., 2021

2020
Selecting Algorithms Without Meta-features.
Proceedings of the Pattern Recognition. ICPR International Workshops and Challenges, 2020

2018
High-Accuracy Scene Recognition and Its Application to Highly-Safe Intelligent Systems.
Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics, 2018

CNOT-Measure Quantum Neural Networks.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

2017
Context Based Visual Content Verification.
CoRR, 2017

Building a Completely Reversible Computer.
CoRR, 2017

Live-feeling communication: Multi-algorithm approach to the estimation of human intentions.
Proceedings of the 2017 IEEE International Conference on Systems, Man, and Cybernetics, 2017

Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

2016
On Minimal Accuracy Algorithm Selection in Computer Vision and Intelligent Systems.
CoRR, 2016

Reasoning and Algorithm Selection Augmented Symbolic Segmentation.
CoRR, 2016

2015
Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path.
IEEE Trans. Very Large Scale Integr. Syst., 2015

An algorithm selection based platform for image understanding using high-level symbolic feedback and machine learning.
Int. J. Mach. Learn. Cybern., 2015

Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Symbolic Segmentation Using Algorithm Selection.
CoRR, 2015

Novel VLSI Architectures for Real-World Intelligent Systems.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

2014
Reversible, Information-Preserving Logic and Its Application.
J. Multiple Valued Log. Soft Comput., 2014

FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation.
J. Comput. Eng., 2014

Synthesis of Quantum Arrays from Kronecker Functional Lattice Diagrams.
IEICE Trans. Inf. Syst., 2014

Implementation of Voltage-Mode/Current-Mode Hybrid Circuits for a Low-Power Fine-Grain Reconfigurable VLSI.
IEICE Trans. Electron., 2014

Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network.
IEICE Trans. Inf. Syst., 2014

Analysis of Faults in Reversible Computing.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Minimizing Reversible Circuits in the 2n Scheme Using Two and Three Bits Patterns.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures.
J. Multiple Valued Log. Soft Comput., 2013

Quantum Finite State Machines - a Circuit Based Approach.
Int. J. Unconv. Comput., 2013

Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Architecture of an Asynchronous FPGA for Handshake-Component-Based Design.
IEICE Trans. Inf. Syst., 2013

A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits.
IEICE Trans. Electron., 2013

A Bit-Serial Reconfigurable VLSI Based on a Multiple-Valued X-Net Data Transfer Scheme.
IEICE Trans. Inf. Syst., 2013

RFID-based localization with Non-Blocking tag scanning.
Ad Hoc Networks, 2013

Analysis of Reversible and Quantum Finite State Machines Using Homing, Synchronizing and Distinguishing Input Sequences.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Multiple-Valued Reversible Benchmarks and Extensible Quantum Specification (XQS) Format.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

An Area-Efficient Multiple-Valued Reconfigurable VLSI Architecture Using an X-Net.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Low-Power Multiple-Valued Source-Coupled Logic Circuits Using Dual-Supply Voltages for a Reconfigurable VLSI.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Bayesian Network for algorithm selection: Real-world hierarchy for nodes reduction.
Proceedings of the International Joint Conference on Awareness Science and Technology & Ubi-Media Computing, 2013

Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

2012
High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level Parallelization vs. Representation?
J. Multiple Valued Log. Soft Comput., 2012

A Digit-Serial Reconfigurable VLSI Based on Quaternary Inter-Cell Data Transfer Scheme.
J. Multiple Valued Log. Soft Comput., 2012

Driver's Intention Estimation Based on Bayesian Networks for a Highly-Safe Intelligent Vehicle.
J. Robotics Mechatronics, 2012

Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates.
IEICE Trans. Electron., 2012

Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors.
IEICE Trans. Inf. Syst., 2012

Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation.
IEICE Trans. Electron., 2012

Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme.
Proceedings of the International SoC Design Conference, 2012

Unified Current-Source Control for Low-Power Current-Mode-Logic Bit-Serial Circuits.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Current-Source-Sharing Differential-Pair Circuits for a Low-Power Fine-Grain Reconfigurable VLSI Architecture.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors.
IEEE Trans. Circuits Syst. Video Technol., 2011

Adaptive Group-Based Job Scheduling for High Performance and Reliable Volunteer Computing.
J. Inf. Process., 2011

Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture.
IEICE Trans. Electron., 2011

Evolutionary Quantum Logic Synthesis of Boolean Reversible Logic Circuits Embedded in Ternary Quantum Space using Heuristics
CoRR, 2011

Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

Non-blocking tag scanning for passive RFID localization.
Proceedings of the 11th International Conference on Intelligent Systems Design and Applications, 2011

High Performance Tag Singulation for Memory-Less RFID Systems.
Proceedings of IEEE International Conference on Communications, 2011

An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits.
IEICE Trans. Inf. Syst., 2010

Group Testing Based Detection of Web Service DDoS Attackers.
IEICE Trans. Commun., 2010

Foreword.
IEICE Trans. Inf. Syst., 2010

An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture.
IEICE Trans. Electron., 2010

A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals.
IEICE Trans. Inf. Syst., 2010

Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

Adaptive Selection of Intelligent Processing Modules and its Applications.
Proceedings of the 2010 International Conference on Artificial Intelligence, 2010

Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

Evolutionary quantum logic synthesis of Boolean reversible logic circuits embedded in ternary quantum space using structural restrictions.
Proceedings of the IEEE Congress on Evolutionary Computation, 2010

2009
Optimal Periodic Memory Allocation for Image Processing With Multiple Windows.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture.
IEICE Trans. Electron., 2009

Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals.
Proceedings of the ISMVL 2009, 2009

Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture.
Proceedings of the ISMVL 2009, 2009

Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

2008
Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment.
IEICE Trans. Electron., 2008

Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation.
IEICE Trans. Electron., 2008

Memory Allocation for Multi-Resolution Image Processing.
IEICE Trans. Inf. Syst., 2008

Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling.
IEICE Trans. Electron., 2008

Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture.
IEICE Trans. Electron., 2008

Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

FPGA implementation of a vehicle detection algorithm using three-dimensional information.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

2007
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits.
J. Multiple Valued Log. Soft Comput., 2007

Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation.
J. Multiple Valued Log. Soft Comput., 2007

Special Section on VLSI Technology toward Frontiers of New Market.
IEICE Trans. Electron., 2007

2006
Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification.
IEICE Trans. Electron., 2006

A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates.
IEICE Trans. Electron., 2006

Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages.
IEEE Trans. Computers, 2005

Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic.
J. Multiple Valued Log. Soft Comput., 2005

Multiple-Valued Logic as a New Computing Paradigm - A Brief Survey of Higuchi's Researchon Multiple-Valued Logic.
J. Multiple Valued Log. Soft Comput., 2005

Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic.
J. Multiple Valued Log. Soft Comput., 2005

Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access.
IEICE Trans. Inf. Syst., 2005

FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Low-Power Field-Programmable VLSI Using Multiple Supply Voltages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic.
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005

Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer.
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005

VLSI architecture based on packet data transfer scheme and its application.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004
Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

2003
Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and its Applications.
J. Multiple Valued Log. Soft Comput., 2003

Optimal Design of a Dual-Rail Multiple-Valued Current-Mode Integrated Circuit Based on Voltage Swing Minimization.
J. Multiple Valued Log. Soft Comput., 2003

Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Multiple-Valued Dynamic Source-Coupled Logic.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

2002
High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

Fully Source-Coupled Logic Based Multiple-Valued VLSI.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

2001
Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources.
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits.
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection.
Proceedings of the 2001 IEEE International Conference on Robotics and Automation, 2001

2000
Design of a VLSI Processor Based on an Immediate Output Generation Scheduling for Ball-Trajectory Prediction.
J. Robotics Mechatronics, 2000

Editorial: Intelligent Integrated Systems for Human-Oriented Information Society.
J. Robotics Mechatronics, 2000

Path Planning Based on Distance Transformation and Its VLSI Implementation.
J. Robotics Mechatronics, 2000

Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture.
J. Robotics Mechatronics, 2000

Architecture of a high-performance stereo vision VLSI processor.
Adv. Robotics, 2000

Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic.
Proceedings of the 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), 2000

Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

1999
Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture.
Systems and Computers in Japan, 1999

Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs.
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999

Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic.
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999

1998
Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application.
Systems and Computers in Japan, 1998

Design and evaluation of a digit-parallel multiple-valued content-addressable memory.
Systems and Computers in Japan, 1998

Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products.
Proceedings of the IEEE International Conference on Robotics and Automation, 1998

1997
Communication network protocol for real-time distributed control and its LSI implementation.
IEEE Trans. Ind. Electron., 1997

A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects.
Systems and Computers in Japan, 1997

One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing.
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

Low-power multiple-valued current-mode integrated circuit with current-source control and its application.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Author's Reply.
IEEE Trans. Computers, 1996

Optimal Design of a VLSI Processor with Spatially and Temporally Parallel Structure.
J. Robotics Mechatronics, 1996

VLSI Processor System for Robotics.
J. Robotics Mechatronics, 1996

Highly-Safe Intelligent Integrated Systems.
J. Robotics Mechatronics, 1996

Editorial: Integration of Intelligence for Robotics in VLSI Chips.
J. Robotics Mechatronics, 1996

Robot Vision VLSI Processor for the Rectangular Solid Representation of 3-Dimensional Objects.
J. Robotics Mechatronics, 1996

Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy.
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

Quaternary Universal-Literal CAM for Cellular Logic Image Processing.
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

1995
Digital Control Parallel VLSI Processor.
J. Robotics Mechatronics, 1995

Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate.
IEICE Trans. Inf. Syst., 1995

Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices.
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic.
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems.
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

1994
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.
IEEE Trans. Computers, 1994

Design of a Model-Based Robot Vision VLSI Processor.
J. Robotics Mechatronics, 1994

Latency Minimization of Parallel VLSI Processors for Robotics Using Integer Programming.
J. Robotics Mechatronics, 1994

Next-Generation Intelligent Integrated Systems Based on Multiple-Valued Digital Processing.
J. Robotics Mechatronics, 1994

Editorial: Intelligent Integrated Systems for Robotics.
J. Robotics Mechatronics, 1994

Architecture of a CAM-Based Collision Detection VLSI Processor for Intelligent Vehicles.
J. Robotics Mechatronics, 1994

Coordinate Transformation VLSI Processor for Redundant Manipulator Control.
J. Robotics Mechatronics, 1994

Design of an Intelligent Fault-Tolerant System for Real-World Applications.
J. Robotics Mechatronics, 1994

Design of Multiple-Valued Linear Digital Circuits for Highly Parallel <i>k</i>-Ary Operations.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

1993
Multi-valued current-mode parallel multiplier based on redundant positive-digit number representations.
Systems and Computers in Japan, 1993

Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations.
Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993

2400-MFLOPS Reconfigurable Parallel VLSI Processor for Robot Control.
Proceedings of the 1993 IEEE International Conference on Robotics and Automation, 1993

1992
Design of an ultrahigher-valued biocomputing system based on set-valued logic networks.
Systems and Computers in Japan, 1992

Interconnection-Free Biomolecular Computing.
Computer, 1992

Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits.
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

Design of a Multiple-Valued VLSI Processor for Digital Control.
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

Residue Arithmetic Based Multiple-Valued VLSI Image Processor.
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

1991
Performance evaluation of a multivalued rsa encryption vlsi.
Systems and Computers in Japan, 1991

Design of a robust fault-tolerant multiplier.
Systems and Computers in Japan, 1991

Design of Interconnection-Free Biomolecular Computing System.
Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991

High-Performance VLSI Processor for Robot Inverse Dynamics Computation.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990
Design of a fault-tolerant arithmetic circuit based on distributed coding and its evaluation.
Systems and Computers in Japan, 1990

Design of an RSA Encryption Processor Based on Signed-Digit Multivalued Arithmetic Circuits.
Systems and Computers in Japan, 1990

Design of a Highly Parallel Ultrahigher-Valued Logic Network Based on a Bio-Device Model.
Systems and Computers in Japan, 1990

Design of a Matrix Multiply-Addition VLSI Processor for Robot control.
J. Robotics Mechatronics, 1990

Editorial: Computer Architecture for Robotics.
J. Robotics Mechatronics, 1990

Design of a Parallel Collision Detection Check VLSI Processor for Robot Manipulator.
J. Robotics Mechatronics, 1990

Robot Electronics System.
J. Robotics Mechatronics, 1990

Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System.
Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990

Toward the Age of Beyond-Binary Electronics and Systems.
Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990

1989
Bi-directional current-mode basic circuits for the multilevel signed-digit arithmetic and their evaluation.
Systems and Computers in Japan, 1989

VLSI Computer for Robotics.
J. Robotics Mechatronics, 1989

Implementation of a high performance LSI for inverse kinematics computation.
Proceedings of the 1989 IEEE International Conference on Robotics and Automation, 1989

1988
Design of a Fault-Tolerant System Based on Knowledge-Engineering Approach and Its Application to a Digital Control System.
Systems and Computers in Japan, 1988

Design of a time-optimal digital control system for a dc-servomotor with amplitude limitation.
Systems and Computers in Japan, 1988

A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits.
Computer, 1988

1987
Design of micropower CMOS quaternary memory circuits.
Systems and Computers in Japan, 1987

Design of VLSI-oriented radix-4 signed-digit arithmetic circuits using multiple-valued logic.
Systems and Computers in Japan, 1987

Design and implementation of an nmos image processor based on quaternary logic.
Systems and Computers in Japan, 1987

1986
Design of low-power quaternary CMOS logic circuits.
Systems and Computers in Japan, 1986

Design of lsi-oriented digital signal processing system Based on Pulse-Train Residue Arithmetic Circuits.
Systems and Computers in Japan, 1986

1977
Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module.
IEEE Trans. Computers, 1977

Static-Hazard-Free <i>T</i>-Gate for Ternary Memory Element and Its Application to Ternary Counters.
IEEE Trans. Computers, 1977


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