Michitaka Kameyama
Orcid: 0000-0002-4245-9907
According to our database1,
Michitaka Kameyama
authored at least 211 papers
between 1977 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1997, "For contributions to the development of multiple-valued intelligent integrated systems.".
Timeline
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On csauthors.net:
Bibliography
2023
Proceedings of the International Conference on Information and Digital Technologies, 2023
2022
Proceedings of the Computational Science - ICCS 2022, 2022
2021
J. Circuits Syst. Comput., 2021
2020
Proceedings of the Pattern Recognition. ICPR International Workshops and Challenges, 2020
2018
High-Accuracy Scene Recognition and Its Application to Highly-Safe Intelligent Systems.
Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics, 2018
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
2017
Live-feeling communication: Multi-algorithm approach to the estimation of human intentions.
Proceedings of the 2017 IEEE International Conference on Systems, Man, and Cybernetics, 2017
Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017
2016
CoRR, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
An algorithm selection based platform for image understanding using high-level symbolic feedback and machine learning.
Int. J. Mach. Learn. Cybern., 2015
Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
2014
J. Multiple Valued Log. Soft Comput., 2014
FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation.
J. Comput. Eng., 2014
IEICE Trans. Inf. Syst., 2014
Implementation of Voltage-Mode/Current-Mode Hybrid Circuits for a Low-Power Fine-Grain Reconfigurable VLSI.
IEICE Trans. Electron., 2014
Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network.
IEICE Trans. Inf. Syst., 2014
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures.
J. Multiple Valued Log. Soft Comput., 2013
Int. J. Unconv. Comput., 2013
Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
IEICE Trans. Inf. Syst., 2013
A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits.
IEICE Trans. Electron., 2013
A Bit-Serial Reconfigurable VLSI Based on a Multiple-Valued X-Net Data Transfer Scheme.
IEICE Trans. Inf. Syst., 2013
Analysis of Reversible and Quantum Finite State Machines Using Homing, Synchronizing and Distinguishing Input Sequences.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Multiple-Valued Reversible Benchmarks and Extensible Quantum Specification (XQS) Format.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Low-Power Multiple-Valued Source-Coupled Logic Circuits Using Dual-Supply Voltages for a Reconfigurable VLSI.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Proceedings of the International Joint Conference on Awareness Science and Technology & Ubi-Media Computing, 2013
Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
Proceedings of the Intelligent Robots and Computer Vision XXX: Algorithms and Techniques, 2013
2012
High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level Parallelization vs. Representation?
J. Multiple Valued Log. Soft Comput., 2012
A Digit-Serial Reconfigurable VLSI Based on Quaternary Inter-Cell Data Transfer Scheme.
J. Multiple Valued Log. Soft Comput., 2012
Driver's Intention Estimation Based on Bayesian Networks for a Highly-Safe Intelligent Vehicle.
J. Robotics Mechatronics, 2012
IEICE Trans. Electron., 2012
Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors.
IEICE Trans. Inf. Syst., 2012
Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation.
IEICE Trans. Electron., 2012
Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme.
Proceedings of the International SoC Design Conference, 2012
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Current-Source-Sharing Differential-Pair Circuits for a Low-Power Fine-Grain Reconfigurable VLSI Architecture.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors.
IEEE Trans. Circuits Syst. Video Technol., 2011
Adaptive Group-Based Job Scheduling for High Performance and Reliable Volunteer Computing.
J. Inf. Process., 2011
Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture.
IEICE Trans. Electron., 2011
Evolutionary Quantum Logic Synthesis of Boolean Reversible Logic Circuits Embedded in Ternary Quantum Space using Heuristics
CoRR, 2011
Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
Proceedings of the 11th International Conference on Intelligent Systems Design and Applications, 2011
Proceedings of IEEE International Conference on Communications, 2011
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits.
IEICE Trans. Inf. Syst., 2010
IEICE Trans. Commun., 2010
IEICE Trans. Electron., 2010
A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals.
IEICE Trans. Inf. Syst., 2010
Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010
Adaptive Selection of Intelligent Processing Modules and its Applications.
Proceedings of the 2010 International Conference on Artificial Intelligence, 2010
Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010
Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010
An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010
Evolutionary quantum logic synthesis of Boolean reversible logic circuits embedded in ternary quantum space using structural restrictions.
Proceedings of the IEEE Congress on Evolutionary Computation, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture.
IEICE Trans. Electron., 2009
Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals.
Proceedings of the ISMVL 2009, 2009
Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture.
Proceedings of the ISMVL 2009, 2009
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009
2008
Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment.
IEICE Trans. Electron., 2008
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation.
IEICE Trans. Electron., 2008
IEICE Trans. Inf. Syst., 2008
IEICE Trans. Electron., 2008
Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture.
IEICE Trans. Electron., 2008
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
FPGA implementation of a vehicle detection algorithm using three-dimensional information.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008
Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008
2007
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits.
J. Multiple Valued Log. Soft Comput., 2007
J. Multiple Valued Log. Soft Comput., 2007
IEICE Trans. Electron., 2007
2006
Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification.
IEICE Trans. Electron., 2006
IEICE Trans. Electron., 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages.
IEEE Trans. Computers, 2005
Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic.
J. Multiple Valued Log. Soft Comput., 2005
Multiple-Valued Logic as a New Computing Paradigm - A Brief Survey of Higuchi's Researchon Multiple-Valued Logic.
J. Multiple Valued Log. Soft Comput., 2005
Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic.
J. Multiple Valued Log. Soft Comput., 2005
Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access.
IEICE Trans. Inf. Syst., 2005
FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic.
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
2004
IEEE J. Solid State Circuits, 2004
Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
2003
J. Multiple Valued Log. Soft Comput., 2003
Optimal Design of a Dual-Rail Multiple-Valued Current-Mode Integrated Circuit Based on Voltage Swing Minimization.
J. Multiple Valued Log. Soft Comput., 2003
Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
2002
High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002
Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002
2001
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001
Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits.
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001
Proceedings of the 2001 IEEE International Conference on Robotics and Automation, 2001
2000
Design of a VLSI Processor Based on an Immediate Output Generation Scheduling for Ball-Trajectory Prediction.
J. Robotics Mechatronics, 2000
J. Robotics Mechatronics, 2000
J. Robotics Mechatronics, 2000
J. Robotics Mechatronics, 2000
Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic.
Proceedings of the 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), 2000
Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
1999
Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture.
Syst. Comput. Jpn., 1999
Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs.
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999
Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic.
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999
1998
Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application.
Syst. Comput. Jpn., 1998
Design and evaluation of a digit-parallel multiple-valued content-addressable memory.
Syst. Comput. Jpn., 1998
Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products.
Proceedings of the IEEE International Conference on Robotics and Automation, 1998
1997
Communication network protocol for real-time distributed control and its LSI implementation.
IEEE Trans. Ind. Electron., 1997
A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects.
Syst. Comput. Jpn., 1997
One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing.
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997
Low-power multiple-valued current-mode integrated circuit with current-source control and its application.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
IEEE J. Solid State Circuits, 1996
IEEE J. Solid State Circuits, 1996
J. Robotics Mechatronics, 1996
J. Robotics Mechatronics, 1996
Robot Vision VLSI Processor for the Rectangular Solid Representation of 3-Dimensional Objects.
J. Robotics Mechatronics, 1996
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996
1995
A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic.
IEEE J. Solid State Circuits, November, 1995
IEICE Trans. Inf. Syst., 1995
Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices.
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic.
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995
1994
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.
IEEE Trans. Computers, 1994
Latency Minimization of Parallel VLSI Processors for Robotics Using Integer Programming.
J. Robotics Mechatronics, 1994
Next-Generation Intelligent Integrated Systems Based on Multiple-Valued Digital Processing.
J. Robotics Mechatronics, 1994
J. Robotics Mechatronics, 1994
Architecture of a CAM-Based Collision Detection VLSI Processor for Intelligent Vehicles.
J. Robotics Mechatronics, 1994
J. Robotics Mechatronics, 1994
J. Robotics Mechatronics, 1994
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel <i>k</i>-Ary Operations.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994
Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994
1993
Multi-valued current-mode parallel multiplier based on redundant positive-digit number representations.
Syst. Comput. Jpn., 1993
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations.
Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993
Proceedings of the 1993 IEEE International Conference on Robotics and Automation, 1993
1992
Design of an ultrahigher-valued biocomputing system based on set-valued logic networks.
Syst. Comput. Jpn., 1992
Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits.
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992
1991
Syst. Comput. Jpn., 1991
Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
1990
Design of a fault-tolerant arithmetic circuit based on distributed coding and its evaluation.
Syst. Comput. Jpn., 1990
Design of an RSA Encryption Processor Based on Signed-Digit Multivalued Arithmetic Circuits.
Syst. Comput. Jpn., 1990
Design of a Highly Parallel Ultrahigher-Valued Logic Network Based on a Bio-Device Model.
Syst. Comput. Jpn., 1990
J. Robotics Mechatronics, 1990
J. Robotics Mechatronics, 1990
Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System.
Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990
Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990
1989
Bi-directional current-mode basic circuits for the multilevel signed-digit arithmetic and their evaluation.
Syst. Comput. Jpn., 1989
Proceedings of the 1989 IEEE International Conference on Robotics and Automation, 1989
1988
Design of a Fault-Tolerant System Based on Knowledge-Engineering Approach and Its Application to a Digital Control System.
Syst. Comput. Jpn., 1988
Design of a time-optimal digital control system for a dc-servomotor with amplitude limitation.
Syst. Comput. Jpn., 1988
Computer, 1988
1987
Design of VLSI-oriented radix-4 signed-digit arithmetic circuits using multiple-valued logic.
Syst. Comput. Jpn., 1987
Syst. Comput. Jpn., 1987
1986
Design of lsi-oriented digital signal processing system Based on Pulse-Train Residue Arithmetic Circuits.
Syst. Comput. Jpn., 1986
1977
Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module.
IEEE Trans. Computers, 1977
Static-Hazard-Free <i>T</i>-Gate for Ternary Memory Element and Its Application to Ternary Counters.
IEEE Trans. Computers, 1977