Shuguo Li

Orcid: 0000-0002-1746-7112

According to our database1, Shuguo Li authored at least 55 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Design an Efficient FPGA-Based Accelerator for Leveled BFV Homomorphic Encryption.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

Hardware Acceleration and Implementation of Fully Homomorphic Encryption Over the Torus.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

Split-Radix Based Compact Hardware Architecture for CRYSTALS-Kyber.
IEEE Trans. Computers, January, 2024

2023
Highly-Efficient Hardware Architecture for CRYSTALS-Kyber With a Novel Conflict-Free Memory Access Pattern.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023

2022
An Efficient Implementation of KYBER.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Optimized Interpolation of Four-Term Karatsuba Multiplication and a Method of Avoiding Negative Multiplicands.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021
Design and Analysis of Approximate 4-2 Compressors for High-Accuracy Multipliers.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Fast Binary Counters and Compressors Generated by Sorting Network.
IEEE Trans. Very Large Scale Integr. Syst., 2021

A Compact Hardware Implementation of CCA-Secure Key Exchange Mechanism CRYSTALS-KYBER on FPGA.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

High-Performance Constant-Time Discrete Gaussian Sampling.
IEEE Trans. Computers, 2021

A Multibit Left-Shift Modular Inverse Hardware Algorithm and its Implementation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Area-Efficient Modular Reduction Structure and Memory Access Scheme for NTT.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
An Efficient Implementation of the NewHope Key Exchange on FPGAs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

RLWE-Oriented High-Speed Polynomial Multiplier Utilizing Multi-Lane Stockham NTT Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Low-Latency and Low-Cost Montgomery Modular Multiplier Based on NLP Multiplication.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A High-Throughput Hardware Implementation of SHA-256 Algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A New Implementation of 16-bit Parallel Prefix Adder for High Speed and Low Area.
Proceedings of the ICDSP 2020: 4th International Conference on Digital Signal Processing, 2020

A Binary Counter Based on Stacking and Sorting.
Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020

A Novel Method of Modular Multiplication Based on Karatsuba-like Multiplication.
Proceedings of the 27th IEEE Symposium on Computer Arithmetic, 2020

2019
A Division-Free Toom-Cook Multiplication-Based Montgomery Modular Multiplication.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Accelerating an FHE Integer Multiplier Using Negative Wrapped Convolution and Ping-Pong FFT.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

High-Speed ECC Processor Over NIST Prime Fields Applied With Toom-Cook Multiplication.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Generalized RNS Mclaughlin Modular Multiplication with Non-Coprime Moduli Sets.
IEEE Trans. Computers, 2019

A Design and Implementation of Montgomery Modular Multiplier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
High-Performance Pipelined Architecture of Point Multiplication on Koblitz Curves.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Improved Algorithms and Implementations for Integer to τ NAF Conversion for Koblitz Curves.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Modular Multiplier Implemented With Truncated Multiplication.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

An Implementation of Karatsuba-based Montgomery Modular Multiplication with Only Half-size Additions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Lazy Reduction and Multi-Precision Division Based on Modular Reductions.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Design of an Area-Effcient Million-Bit Integer Multiplier Using Double Modulus NTT.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Base Extent Optimization for RNS Montgomery Algorithm.
Proceedings of the 2017 IEEE Trustcom/BigDataSE/ICESS, Sydney, Australia, August 1-4, 2017, 2017

A High-Speed and SPA-Resistant Implementation of ECC Point Multiplication Over GF(p).
Proceedings of the 2017 IEEE Trustcom/BigDataSE/ICESS, Sydney, Australia, August 1-4, 2017, 2017

A Reconfigurable High-Speed ECC Processor Over NIST Primes.
Proceedings of the 2017 IEEE Trustcom/BigDataSE/ICESS, Sydney, Australia, August 1-4, 2017, 2017

A design for high speed leading-zero counter.
Proceedings of the IEEE International Symposium on Consumer Electronics, 2017

Design of a fast number theoretical transform engine for fully homomorphic encryption.
Proceedings of the IEEE International Symposium on Consumer Electronics, 2017

A new digital true random number generator based on delay chain feedback loop.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Fast inversion in GF(2m) with polynomial basis using optimal addition chains.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 3DES implementation especially for CBC feedback loop mode.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Fast RNS implementation of elliptic curve point multiplication in GF(p) with selected base pairs.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

High throughput AES encryption/decryption with efficient reordering and merging techniques.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Broken-Karatsuba multiplication and its application to Montgomery modular multiplication.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Determine the carry bit of carry-sum generated by unsigned MBE multiplier without final addition.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2<sup>m</sup>).
IEEE Trans. Very Large Scale Integr. Syst., 2016

A High-Speed Digital True Random Number Generator Based on Cross Ring Oscillator.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

The ASIC Implementation of SM3 Hash Algorithm for High Throughput.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

2015
A High Performance FPGA Implementation of 256-bit Elliptic Curve Cryptography Processor Over GF(<i>p</i>).
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Fast RSA decryption through high-radix scalable Montgomery modular multipliers.
Sci. China Inf. Sci., 2015

2014
A Digital TRNG Based on Cross Feedback Ring Oscillators.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

2013
Fast, compact and symmetric modular exponentiation architecture by common-multiplicand Montgomery modular multiplications.
Integr., 2013

2011
CSA-based design of feedforward scalable montgomery modular multiplier.
Proceedings of the 2011 IEEE International Symposium on Signal Processing and Information Technology, 2011

2010
Random numbers from an integrated CMOS double-scroll.
IEICE Electron. Express, 2010

2009
Data-recovery algorithm and circuit for cyclic convolution based on FNT.
IEICE Electron. Express, 2009

Efficient FPGA implementation of sharp FIR filters using the FRM technique.
IEICE Electron. Express, 2009

Area-delay efficient parallel architecture for Fermat number transform.
IEICE Electron. Express, 2009

High Speed Parallel Architecture for Cyclic Convolution Based on FNT.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009


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