Shunichi Toida

According to our database1, Shunichi Toida authored at least 15 papers between 1969 and 2006.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2006
Preposition Senses: Generalized Disambiguation Model.
Proceedings of the Computational Linguistics and Intelligent Text Processing, 2006

1994
On Polynomial-Time Testable Combinational Circuits.
IEEE Trans. Computers, 1994

1993
Revisiting shift register realization for ease of test generation and testing.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

1992
On test generation for combinational circuits consisting of AND and EXOR gates.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Computational Complexity of Test-Point Insertions and Decompositions.
Proceedings of the Fifth International Conference on VLSI Design, 1992

1991
On polynomial-time testable classes of combinational circuits.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

1982
The Complexity of Fault Detection Problems for Combinational Logic Circuits.
IEEE Trans. Computers, 1982

1981
On Minimal Test Sets for Locating Single Link Failures in Networks.
IEEE Trans. Computers, 1981

1977
A note on Ádám's conjecture.
J. Comb. Theory, Ser. B, 1977

1976
System Diagnosis and Redundant Tests.
IEEE Trans. Computers, 1976

1975
A Diagnosing Algorithm for Networks
Inf. Control., October, 1975

An Approach to the Diagnosability Analysis of a System.
IEEE Trans. Computers, 1975

1973
Generation of all Cutsets of a Bipath Network.
IEEE Trans. Commun., 1973

Efficient Algorithms for Determining an Extremal Tree of a Graph (Extended Abstract)
Proceedings of the 14th Annual Symposium on Switching and Automata Theory, 1973

1969
A Characterization of Biplanar Graphs
PhD thesis, 1969


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