Siamak Delshadpour

According to our database1, Siamak Delshadpour authored at least 16 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
A PMOS Switch Body and Gate Control Circuit for USB3.2 Compliant Receiver.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A 20.6 Gb/s Programmable Peaking Gain CTLE.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A 0.7 μw Explicit Bandgap Less POR Circuit With Brownout Detection.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

A Type-C USB Power Delivery Chip Faced Catastrophic Failure.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

A PLL Based FSK Demodulator With Auxiliary Path.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Multiple Power System for Type-C USB Power Delivery.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
A 5.4 Gbps Protocol Based CMOS Limiting ReDriver for Type-C Applications.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A 2.6 MHz Bandwidth, 3<sup>rd</sup>/5<sup>th</sup> Order Active-RC Polyphase Filter with Quadrature Offset Cancellation for Low-IF GPS Radio.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Programmable Order Multiple Feedback Band-Pass Active-RC filter for FSK Transceiver.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

A BMC Analog/Digital PHY for Type-C USB Power Delivery Chip in 0.14 μm CMOS Technology.
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019

A 5.4 Gbps Type-C USB3.1/DP1.2 Combo Limiting ReDriver in 0.14 μm CMOS Technology.
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019

2018
Low Power 20.625 Gbps Type-C USB3.2/DPl.4/ Thunderbolt3 Combo Linear Redriver in 0.25 μm BiCMOS Technology.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

An FSK Transceiver for USB Power Delivery in 0.14-μm CMOS Technology.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

A 64 dB Dynamic Range Programmable Gain Amplifier for Dual Band WLAN 802.11abg IF Receiver in 0.18 μm CMOS Technology.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

A Low Power CMOS gm-C Polyphase Filter for Low-IF GPS Receiver.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2008
A Spur Elimination Technique for Phase Interpolation-Based Fractional-N PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008


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