Siva Kumar Rapina

According to our database, Siva Kumar Rapina authored at least 3 papers between 2023 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

8GHz Multi-Phase Ring VCO Design with Wide Tuning Range for SerDes Applications in 6nm FinFET Process.

Ravuru Vasudeva Reddy, Siva Kumar Rapina, Siddhartha Hazra, K. Sarangam

Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

2024

Phase frequency detector with zero-reset pulse for low-spur Phase-locked loop applications.

Marichamy Divya, Siva Kumar Rapina, S. Kumaravel

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

A 16Gbps 3rd Order CTLE Design for Serial Links with High Channel Loss in 16nm FinFET.

Thota Pranay Kumar, Siva Kumar Rapina, Bheema Rao Nistala

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023