Sivaraman Masilamani

According to our database, Sivaraman Masilamani authored at least 2 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

21.5 A Fully Integrated Multi-Phase Voltage Regulator with Enhanced Light-Load-Efficiency Peak of 86%, Featuring an Autonomous Mode Transition from Hard-Switching to Soft-Switching to Discontinuous Conduction Mode in 3nm FinFET CMOS.

Kishan Joshi, Avinash Shreepathi Bhat, Christopher Schaef, Keng Chen, Edward Lee, Yura Kocharyan, Ajay Janardanan, Dinesh Ganta, Huanhuan Zhang, Maximilian Geppert, Prescott McLaughlin, Arvind Raghavan, Sivaraman Masilamani, Syed Askari, Kelly Livingston

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

A Fully Integrated 1 GHz 8A I_max Step-Down and Step-Up Switched Capacitor Voltage Regulator in 3 nm FinFET Technology Featuring Auto Mode Transition.

Arvind Raghavan, Keng Chen, Huanhuan Zhang, Sivaraman Masilamani, Tamir Salus, Rachid Rayess, Gayathri Devi Sridharan, Aruna Payala, Jianrong Chen

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2024