Sivaraman Masilamani

According to our database, Sivaraman Masilamani authored at least 4 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

A Fully Integrated Gate-All-Around Ribbon FET Based Dual-Loop 1 GHz Switched-Capacitor Voltage Regulator with Anti-Leakage, Adaptive Dead Time and Self-Discharge Features.

Arvind Raghavan, Sivaraman Masilamani, Keng Chen, Huanhuan Zhang, Tamir Salus, Rachid Rayess

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025

Fully Integrated Two-Phase Dual Rails Charge Pump Design in Gate-All-Around (GAA) Ribbon FET Process Technology.

Huanhuan Zhang, Keng Chen, Arvind Raghavan, Yura Kocharyan, Sivaraman Masilamani

IEEE Access, 2025

21.5 A Fully Integrated Multi-Phase Voltage Regulator with Enhanced Light-Load-Efficiency Peak of 86%, Featuring an Autonomous Mode Transition from Hard-Switching to Soft-Switching to Discontinuous Conduction Mode in 3nm FinFET CMOS.

Kishan Joshi, Avinash Shreepathi Bhat, Christopher Schaef, Keng Chen, Edward Lee, Yura Kocharyan, Ajay Janardanan, Dinesh Ganta, Huanhuan Zhang, Maximilian Geppert, Prescott McLaughlin, Arvind Raghavan, Sivaraman Masilamani, Syed Askari, Kelly Livingston

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

A Fully Integrated 1 GHz 8A I_max Step-Down and Step-Up Switched Capacitor Voltage Regulator in 3 nm FinFET Technology Featuring Auto Mode Transition.

Arvind Raghavan, Keng Chen, Huanhuan Zhang, Sivaraman Masilamani, Tamir Salus, Rachid Rayess, Gayathri Devi Sridharan, Aruna Payala, Jianrong Chen

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2024