Sri Harsh Pakala

Orcid: 0000-0003-2942-0546

According to our database1, Sri Harsh Pakala authored at least 8 papers between 2012 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2019
A Spread-Spectrum Mode Enabled Ripple-Based Buck Converter Using a Clockless Frequency Control.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

2017
A hybrid voltage-mode hysteretic boost converter with high efficiency across a wide load range.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

High bandwidth class-AB amphfier with high slew rate and fast current sensing for envelope tracking applications.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A multi-loop low-dropout FVF voltage regulator with enhanced load regulation.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2015
Voltage buffer compensation using Flipped Voltage Follower in a two-stage CMOS op-amp.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

2013
Elimination of false codes in an asynchronous parallel successive approximation A/D converter.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A 5.3µA quiescent current fully-integrated low-dropout (LDO) regulator with Transient Recovery Time Enhancement.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2012
A 22dB PSRR enhancement in a two-stage CMOS opamp using tail compensation.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012


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