Annajirao Garimella

According to our database, Annajirao Garimella authored at least 14 papers between 2003 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

Flipped Voltage Follower Based Low Dropout (LDO) Voltage Regulators: A Tutorial Overview.

Punith R. Surkanti, Annajirao Garimella, Paul M. Furth

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2017

On the analysis of low output impedance characteristic of flipped voltage follower (FVF) and FVF LDOs.

Punith R. Surkanti, Annajirao Garimella, Mahender Manda, Paul M. Furth

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2015

Voltage buffer compensation using Flipped Voltage Follower in a two-stage CMOS op-amp.

Sri Harsh Pakala, Mahender Manda, Punith R. Surkanti, Annajirao Garimella, Paul M. Furth

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

2012

Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview.

Annajirao Garimella, Punith R. Surkanti, Paul M. Furth

Proceedings of the 25th International Conference on VLSI Design, 2012

Embedded Tutorial ET1: Pole-Zero Analysis of Low-Dropout (LDO) Regulators: A Tutorial Overview.

Annajirao Garimella, Punith R. Surkanti, Paul M. Furth

Proceedings of the 25th International Conference on VLSI Design, 2012

Low dropout (LDO) voltage regulator design using split-length compensation.

Paul M. Furth, Nitya R. Thota, Venkat Harish Nammi, Annajirao Garimella

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A 22dB PSRR enhancement in a two-stage CMOS opamp using tail compensation.

Paul M. Furth, Sri Harsh Pakala, Annajirao Garimella, Chaitanya Mohan

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2010

Reverse Nested Miller Compensation Using Current Buffers in a Three-Stage LDO.

Annajirao Garimella, M. Wasequr Rashid, Paul M. Furth

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Single Miller compensation using inverting current buffer for multi-stage amplifiers.

Annajirao Garimella, M. Wasequr Rashid, Paul M. Furth

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

A 1.21V, 100mA, 0.1µF-10µF output capacitor low drop-out voltage regulator for SoC applications.

Annajirao Garimella, Paul M. Furth

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators.

Jaime Ramírez-Angulo, Lalitha Mohana Kalyani-Garimella, Annajirao Garimella, Sri Raga Sudha Garimella, Antonio J. López-Martín, Ramón González Carvajal

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007

Low voltage gain boosting schemes for one stage operational amplifiers.

Jaime Ramírez-Angulo, Annajirao Garimella, Lalitha Mohana Kalyani-Garimella, Milind S. Sawant, Antonio Lopez-Martin, Ramón González Carvajal

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006

Low-Voltage Universal Cell (LVUC): A Compact Analog/Digital Logic Block for Mixed Signal FPGAs.

Lalitha Mohana Kalyani-Garimella, Annajirao Garimella, Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2003

VLSI Implementation of Online Digital Watermarking Technique with Difference Encoding for 8-Bit Gray Scale Images.

Annajirao Garimella, M. V. V. Satyanarayana, R. Satish Kumar, P. S. Murugesh, U. C. Niranjan

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003