Subramanian K. Iyer

According to our database1, Subramanian K. Iyer authored at least 10 papers between 2001 and 2006.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2006
On partitioning and symbolic model checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2005
Under-approximation Heuristics for Grid-based Bounded Model Checking.
Proceedings of the 4th International Workshop on Parallel and Distributed Methods in Verification, 2005

Multi-threaded reachability.
Proceedings of the 42nd Design Automation Conference, 2005

Predictive Reachability Using a Sample-Based Approach.
Proceedings of the Correct Hardware Design and Verification Methods, 2005

Error Detection Using BMC in a Parallel Environment.
Proceedings of the Correct Hardware Design and Verification Methods, 2005

A New Reachability Algorithm for Symmetric Multi-processor Architecture.
Proceedings of the Automated Technology for Verification and Analysis, 2005

Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
A Partitioning Methodology for BDD-Based Verification.
Proceedings of the Formal Methods in Computer-Aided Design, 5th International Conference, 2004

2003
Improved Symbolic Verification Using Partitioning Techniques.
Proceedings of the Correct Hardware Design and Verification Methods, 2003

2001
The MacBeth Specification, Modeling and Programming Language.
Proceedings of the 7th IEEE Real-Time Technology and Applications Symposium (RTAS 2001), 30 May, 2001


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