Jawahar Jain

According to our database, Jawahar Jain authored at least 45 papers between 1991 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2013

Comparing stress markers across various cohorts in a mobile setting.

Shreyans Gandhi, Jawahar Jain, Maryam Shojaei Baghini, Soumyo Mukherji

Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

Optimizing BDDs for time-series dataset manipulation.

Stergios Stergiou, Jawahar Jain

Proceedings of the Design, Automation and Test in Europe, 2013

2010

Dynamically resizable binary decision diagrams.

Stergios Stergiou, Jawahar Jain

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2008

Optimizing routing tables on systems-on-chip with Content-Addressable Memories.

Stergios Stergiou, Jawahar Jain

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

2006

On partitioning and symbolic model checking.

Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Disjunctive Transition Relation Decomposition for Efficient Reachability Analysis.

Stergios Stergiou, Jawahar Jain

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2005

Under-approximation Heuristics for Grid-based Bounded Model Checking.

Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, E. Allen Emerson

Proceedings of the 4th International Workshop on Parallel and Distributed Methods in Verification, 2005

Multi-threaded reachability.

Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson

Proceedings of the 42nd Design Automation Conference, 2005

Predictive Reachability Using a Sample-Based Approach.

Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson

Proceedings of the Correct Hardware Design and Verification Methods, 2005

Error Detection Using BMC in a Parallel Environment.

Subramanian K. Iyer, Jawahar Jain, Mukul R. Prasad, Debashis Sahoo, Thomas Sidle

Proceedings of the Correct Hardware Design and Verification Methods, 2005

A New Reachability Algorithm for Symmetric Multi-processor Architecture.

Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill

Proceedings of the Automated Technology for Verification and Analysis, 2005

Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes.

Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, Takeshi Shimizu

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Can SAT be used to Improve Sequential ATPG Methods?

Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Partitioning Methodology for BDD-Based Verification.

Debashis Sahoo, Subramanian K. Iyer, Jawahar Jain, Christian Stangier, Amit Narayan, David L. Dill, E. Allen Emerson

Proceedings of the Formal Methods in Computer-Aided Design, 5th International Conference, 2004

2003

Solving the latch mapping problem in an industrial setting.

Kelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain

Proceedings of the 40th Design Automation Conference, 2003

Improved Symbolic Verification Using Partitioning Techniques.

Subramanian K. Iyer, Debashis Sahoo, Christian Stangier, Amit Narayan, Jawahar Jain

Proceedings of the Correct Hardware Design and Verification Methods, 2003

2002

Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table.

Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita

Formal Methods Syst. Des., 2002

Improving Sequential ATPG Using SAT Methods.

Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

2001

A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs.

Jawahar Jain, Ingo Wegener, Masahiro Fujita

IEEE Trans. Computers, 2001

Practical use of sequential ATPG for model checking: going the extra mile does pay off.

Michael S. Hsiao, Jawahar Jain

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

2000

Testing, Verification, and Diagnosis in the Presence of Unknowns.

Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Hierarchical Error Diagnosis Targeting RTL Circuits.

Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Efficient variable ordering using aBDD based sampling.

Yuan Lu, Jawahar Jain, Edmund M. Clarke, Masahiro Fujita

Proceedings of the 37th Conference on Design Automation, 2000

Analysis of composition complexity and how to obtain smaller canonical graphs.

Jawahar Jain, K. Mohanram, Dinos Moundanos, Ingo Wegener, Yuan Lu

Proceedings of the 37th Conference on Design Automation, 2000

Automatic partitioning for efficient combinatorial verification.

Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita

Proceedings of ASP-DAC 2000, 2000

1999

An efficient filter-based approach for combinational verification.

Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Efficient Scheduling Techniques for ROBDD Construction.

Rajeev Murgai, Jawahar Jain, Masahiro Fujita

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Multiple Error Diagnosis Based on Xlists.

Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni

Proceedings of the 36th Conference on Design Automation, 1999

1998

Sampling schemes for computing OBDD variable orderings.

Jawahar Jain, William Adams, Masahiro Fujita

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997

Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions.

Jawahar Jain, James R. Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell

IEEE Trans. Computers, 1997

Formal Verification of Combinational Circuit.

Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Survey of Techniques for Formal Verification of Combinational Circuits.

Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Reachability analysis using partitioned-ROBDDs.

Amit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

A study of composition schemes for mixed apply/compose based construction of ROBDDs.

Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

On More Efficient Combinational ATPG Using Functional Learning.

Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions.

Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Decomposition Techniques for Efficient ROBDD Construction.

Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita

Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996

1995

Efficient variable ordering and partial representation algorithm.

Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

VERIFUL: VERIfication using FUnctional Learning.

Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita

Proceedings of the 1995 European Design and Test Conference, 1995

Advanced Verification Techniques Based on Learning.

Jawahar Jain, Rajarshi Mukherjee, Masahiro Fujita

Proceedings of the 32st Conference on Design Automation, 1995

1994

Functional learning: a new approach to learning in digital circuits.

Rajarshi Mukherjee, Jawahar Jain, Dhiraj K. Pradhan

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

A new scheme to compute variable orders for binary decision diagrams.

Jawahar Jain, James R. Bitner, Dinos Moundanos, Jacob A. Abraham, Donald S. Fussell

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Efficient Algorithmic Circuit Verification Using Indexed BDDs.

James R. Bitner, Jawahar Jain, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell

Proceedings of the Digest of Papers: FTCS/24, 1994

1992

Probabilistic Verification of Boolean Functions.

Jawahar Jain, Jacob A. Abraham, James R. Bitner, Donald S. Fussell

Formal Methods Syst. Des., 1992

1991

Probabilistic Design Verification.

Jawahar Jain, James R. Bitner, Donald S. Fussell, Jacob A. Abraham

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991