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Sucheta Mohapatra

Orcid: 0000-0003-2200-4224

Affiliations:
  • Portland State University, OR, USA


According to our database1, Sucheta Mohapatra authored at least 5 papers between 2014 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

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Online presence:

On csauthors.net:

Bibliography

2021
Fast Buffer Count Estimation in 3D IC Floorplanning.
[BibTeX]
[DOI]
Sucheta Mohapatra
,
Satya K. Vendra
,
Malgorzata Chrzanowska-Jeske
IEEE Trans. Circuits Syst. II Express Briefs, 2021

2016
Performance optimization and power efficiency in 3D IC with buffer insertion scheme.
[BibTeX]
[DOI]
Mohammad A. Ahmed
,
Sucheta Mohapatra
,
Malgorzata Chrzanowska-Jeske
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Buffered Interconnects in 3D IC Layout Design.
[BibTeX]
[DOI]
Mohammad A. Ahmed
,
Sucheta Mohapatra
,
Malgorzata Chrzanowska-Jeske
Proceedings of the 18th System Level Interconnect Prediction Workshop, 2016

2015
Dynamic nets-to-TSVs assignment in 3D floorplanning.
[BibTeX]
[DOI]
Mohammad A. Ahmed
,
Sucheta Mohapatra
,
Malgorzata Chrzanowska-Jeske
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
3D floorplanning with nets-to-TSVs assignment.
[BibTeX]
[DOI]
Mohammad A. Ahmed
,
Sucheta Mohapatra
,
Malgorzata Chrzanowska-Jeske
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014


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