Sudhanshu Janwadkar

According to our database, Sudhanshu Janwadkar authored at least 4 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2024

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic-Wallace tree multiplier.

Sudhanshu Janwadkar, Rasika Dhavse

Int. J. Circuit Theory Appl., April, 2024

ASIC design of power and area efficient programmable FIR filter using optimized Urdhva-Tiryagbhyam Multiplier for impedance cardiography.

Sudhanshu Janwadkar, Rasika Dhavse

Microprocess. Microsystems, 2024

2022

Investigation and Analysis of Power Performance Area (PPA) Cards of Digital Multiplier Architectures.

Sudhanshu Janwadkar, Rasika Dhavse

J. Circuits Syst. Comput., 2022

2020

Implementation and Performance Evaluation of Novel Line Adder Architecture for Portable Systems : A Vedic Mathematics Approach.

Sudhanshu Janwadkar, Rasika Dhavse

Proceedings of the 2020 IEEE Region 10 Conference, 2020