Sunita M. S

According to our database, Sunita M. S authored at least 7 papers between 2020 and 2026.

Collaborative distances:

• Dijkstra number of seven.
• Erdős number of six.

2026

A Novel 8T SRAM-Based In-Memory Computing Architecture for MAC-Derived Logical Functions.

Amogh K. M, Sunita M. S

Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

2024

High PSR Low Power Negative-R-Assisted LDO.

Soorya V, Sunita M. S

Proceedings of the IEEE Region 10 Conference, 2024

91.2% Efficiency Low Power Non-Inverting Buck-Boost Converter.

Amit Gupta, Sunita M. S

Proceedings of the IEEE Region 10 Conference, 2024

Optimization of Analog Circuit Placement: A Graph Neural Network Approach.

Yogitha H. K., Sinchana K., Shristi Biyani, Sunita M. S

Proceedings of the 2024 10th International Conference on Computing and Artificial Intelligence, 2024

2021

Adaptive ON - Time Boost Converter in 45nm for Solar Cell Applications.

Sunita M. S, Tejas Somashekhar, Shashidhar Tantry

Proceedings of the 18th International SoC Design Conference, 2021

2020

50 MHz 3-Level Buck Converter with added Boost Converter.

Sunita M. S, Mayur G. D, Preet Bedi, Nagesh Verma, Shashidhar Tantry

Proceedings of the International SoC Design Conference, 2020

Comparative analysis of FinFET and Planar MOSFET SRAMs.

Pradeep K, Mohith B, Manjunath K. P, Sunita M. S

Proceedings of the International SoC Design Conference, 2020