Shashidhar Tantry

According to our database, Shashidhar Tantry authored at least 8 papers between 2001 and 2025.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2025

Design of a Low Phase Noise Quadrature DCO Using Dual Superharmonic Injection in 55nm CMOS for Ka-Band Applications.

Devesh Bhaskaran, Shashidhar Tantry

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

2021

Adaptive ON - Time Boost Converter in 45nm for Solar Cell Applications.

Sunita M. S, Tejas Somashekhar, Shashidhar Tantry

Proceedings of the 18th International SoC Design Conference, 2021

2020

50 MHz 3-Level Buck Converter with added Boost Converter.

Sunita M. S, Mayur G. D, Preet Bedi, Nagesh Verma, Shashidhar Tantry

Proceedings of the International SoC Design Conference, 2020

2003

A Low Voltage Floating Resistor Circuit Having Both Positive and Negative Resistance Values.

Shashidhar Tantry, Yasuyuki Hiraku, Takao Oura, Teru Yoneyama, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

2002

A CMOS Floating Resistor Circuit Having Both Positive and Negative Resistance Values.

Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values.

Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A low voltage floating resistor having positive and negative resistance values.

Shashidhar Tantry, Takao Oura, Teru Yoneyama, Hideki Asai

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

Two floating resistor circuits and their applications to synaptic weights in analog neural networks.

Shashidhar Tantry, Teru Yoneyama, Hideki Asai

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001