Supreeth Mysore Shivanandamurthy

According to our database, Supreeth Mysore Shivanandamurthy authored at least 5 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2024

Low-Latency, Energy-Efficient In-DRAM CNN Acceleration with Bit-Parallel Unary Computing.

Ishan G. Thakkar, Supreeth Mysore Shivanandamurthy, Sayed Ahmad Salehi

Proceedings of the Embedded Machine Learning for Cyber-Physical, 2024

2023

AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning.

Supreeth Mysore Shivanandamurthy, Sairam Sri Vatsavai, Ishan G. Thakkar, Sayed Ahmad Salehi

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

2021

ODIN: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-Situ Neural Network Processing in Phase Change RAM.

Supreeth Mysore Shivanandamurthy, Ishan G. Thakkar, Sayed Ahmad Salehi

CoRR, 2021

ATRIA: A Bit-Parallel Stochastic Arithmetic Based Accelerator for In-DRAM CNN Processing.

Supreeth Mysore Shivanandamurthy, Ishan G. Thakkar, Sayed Ahmad Salehi

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2019

A scalable stochastic number generator for phase change memory based in-memory stochastic processing: work-in-progress.

Supreeth Mysore Shivanandamurthy, Ishan G. Thakkar, Sayed Ahmad Salehi

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019