Suraj Kumar Prusty

Orcid: 0000-0002-7604-9156

According to our database1, Suraj Kumar Prusty authored at least 7 papers between 2022 and 2026.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Energy Efficient Clock-Based Summer-Latch for Delay Reduction in DFE-Based Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2026

2024
Energy Efficient Resistor-Transconductor Hybrid-Based Full-Duplex Transceiver for Serial Link.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

Energy Efficient Integrated Summer and Latch-Based DFE With Reduced Tap Loading.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Machine Learning based Adaptation for CTLE of Serial Links.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024

2023
A High-Speed Charge-Injection based Double Tail Latch for Decision Feedback Equalizer (DFE).
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

A 26 Gb/s Echo-Cancellation Based Simultaneous Bidirectional Transceiver in 65 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Current-integrating summer for DFE receiver with low common mode variation.
Microelectron. J., 2022


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