Bibhudatta Sahoo

Orcid: 0000-0002-3563-9096

Affiliations:
  • Indian Institute of Technology Kharagpur, Department of Electronics and Electrical Communication Engineering, Kharagpur, India (since 2017)
  • University of Illinois at Urbana-Champaign, IL, USA (2016 - 2017)
  • Amrita University, Department of Electronics and Communication Engineering, Amiratapuri, India (2012 - 2016)
  • University of California, Los Angeles, CA, USA (PhD 2009)
  • Broadcom, Irvine, CA, USA (2000 - 2007)
  • University of Minnesota-Twin Cities, Minneapolis, MN, USA (1998 - 2000)
  • Indian Institute of Technology, Kharagpur, India (1994 - 1998)


According to our database1, Bibhudatta Sahoo authored at least 50 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Generalized Sampling-Based Multi-Channel Sampling of Signals Realized With Pure Delay Analog Filters and Digital FIR Reconstruction Filters.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023

Transition Point Estimation Using RC-Filtered Square Wave for Calibration of SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2023

Energy-Efficient FPGA Implementation of Power-of-2 Weights-Based Convolutional Neural Networks With Low Bit-Precision Input Images.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

Johnson Counter-Based Multiphase Generation for VCO-Based ADC for Direct Digitization of Low Amplitude Sensor Signals.
IEEE Trans. Instrum. Meas., 2023

IIR Filter-Based Spiking Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Low Power Cyclic ADC Architecture using Reference Scaling Technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Noise Resilience of Reduced Precision Neural Networks.
Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2023

2022
A Dual VCO Based L5/S Band PLL with Extended Range Divider for IRNSS Application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Closed-Form Expression for the Combined Effect of Offset, Gain, Timing, and Bandwidth Mismatch in Time-Interleaved ADCs Using Generalized Sampling.
IEEE Trans. Instrum. Meas., 2021

Performance Limits of Generalized Sampling Based 2-Channel Analog-to-Digital Converter.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Comparison of Real-Valued FFT Architectures for Low-Throughput Applications using FPGA.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

2020
A Low-Power Reconfigurable Narrowband/Wideband LNA for Cognitive Radio-Wireless Sensor Network.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Deterministic Dither Based Mismatch Characterization of Wide Range of Metal-Oxide-Metal Capacitors.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Time-Domain Modeling of Switched-Capacitor Converters with Periodic Inputs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
A Packaged Noise-Canceling High-Gain Wideband Low Noise Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Adder-Only Convolutional Neural Network with Binary Input Image.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Curvature Compensated Bandgap Circuit Exploiting Temperature Dependence of β.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Systematic Approach to Sizing Capacitors in Split-SAR ADC to Achieve Optimum Redundancy.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018
A DC-to-1-GHz Continuously Tunable Bandpass ADC.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A 250-MHz Pipelined ADC-Based f<sub>S</sub>/4 Noise-Shaping Bandpass ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Wideband 2-5 GHz Noise Canceling Subthreshold Low Noise Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Mitigating Aperture Error in Pipelined ADCs Without a Front-end Sample-and-Hold Amplfier.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Wide Input Range Single Feed RF Energy Harvester.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

1-Transistor-1-Memristor Multilevel Memory Cell.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017
Achieving Theoretical Limit of SFDR in Pipelined ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Analysis and Design of Single Reference Reduced Summer Loading-Based Switched Capacitor DFE.
Circuits Syst. Signal Process., 2017

VCO based Nyquist-rate ADC with FVCO of Fs/2.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Ring oscillator based sub-1V leaky integrate-and-fire neuron circuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Thermal noise canceling pipelined ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

CMOS mixed signal SoC for low-side current sensing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 0.7V time-based inductor for fully integrated low bandwidth filter applications.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Thermal-Noise-Canceling Switched-Capacitor Circuit.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A Digitally Assisted Radiation Hardened Current Steering DAC.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Bootstrapped leakage suppression switch for switched capacitor circuits with zero input common mode.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Full-rate switched capacitor multi-tap DFE for long-tail post-cursor cancellation.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

2015
A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application.
Proceedings of the 28th International Conference on VLSI Design, 2015

At speed digital gain error calibration of pipelined ADCs.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

2014
An 8 Bit 4 GS/s 120 mW CMOS ADC.
IEEE J. Solid State Circuits, 2014

Histogram Based Deterministic Digital Background Calibration for Pipelined ADCs.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A multi-pole single-tap IIR based DFE equalizer topology.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

An overview of digital calibration techniques for pipelined ADCs.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013
A 10-b 1-GHz 33-mW CMOS ADC.
IEEE J. Solid State Circuits, 2013

2012
A 10-bit 1-GHz 33-mW CMOS ADC.
Proceedings of the Symposium on VLSI Circuits, 2012

Error feedback based noise shaping in a double sampled ADC.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Radix based digital calibration technique for pipelined ADC using Nyquist sampling of sinusoid.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2009
A 12-Bit 200-MHz CMOS ADC.
IEEE J. Solid State Circuits, 2009

U-PAS: A user-friendly ADC simulator for courses on analog design.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2009

2003
A Low Power Correlator for CDMA Wireless Systems.
J. VLSI Signal Process., 2003

2000
A low-power correlator.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000


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