Surendra S. Rathod

According to our database, Surendra S. Rathod authored at least 16 papers between 2010 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Multiattribute Deep CNN-Based Approach for Detecting Medicinal Plants and Their Use for Skin Diseases.

Prachi Dalvi, Dhananjay R. Kalbande, Surendra Singh Rathod, Harshal Dalvi, Amey Agarwal

IEEE Trans. Artif. Intell., March, 2025

2024

Modelling and design of asynchronous receptive circuit for cone pathways.

Payal Shah, Satvik Sawant, Reena Sonkusare, Surendra S. Rathod

Integr., January, 2024

2021

Automating Camera Rover for Sports Broadcast.

Param Deshpande, Omkar Gaikwad, Manav Jain, Krisha Choksi, Prashant V. Kasambe, Surendra Singh Rathod

Proceedings of the 12th International Conference on Computing Communication and Networking Technologies, 2021

2020

Modelling the Spiking Behaviour of Ganglion Cells.

Anand Verma, Rutwik Pandit, Sushrut Thakur, Ameya Mungekar, Payal Shah, Surendra Singh Rathod

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Suppression of SSN in High-Speed Circuits using 1-D EBG structure.

Sayli Shinde, Manisha Bansode, Pramod P. Bhavarthe, Surendra S. Rathod

Proceedings of the 11th International Conference on Computing, 2020

2019

SOI FinFET based instrumentation amplifier for biomedical applications.

Reena Sonkusare, Omkar Joshi, Surendra S. Rathod

Microelectron. J., 2019

2017

Synapse Circuits Implementation and Analysis in 180 nm MOSFET and CNFET Technology.

Sushma Srivastava, Surendra S. Rathod

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2015

Analysis of CMOS inhibitory synapse with varying neurotransmitter concentration, reuptake time and spread delay.

Pradyumna Galgali, Surendra S. Rathod

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Implementing a cloud based Xilinx ISE FPGA design platform for integrated remote labs.

Jinalkumar Doshi, Pratiksha Patil, Zalak Dave, Ganesh Gore, Jonathan Joshi, Reena Sonkusare, Surendra S. Rathod

Proceedings of the 2015 International Conference on Advances in Computing, 2015

2012

Dg-FinFET-Based SRAM Configurations for Increased SEU Immunity.

Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta

J. Circuits Syst. Comput., 2012

Analysis of double-gate FinFET-based address decoder for radiation-induced single-event-transients.

Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta

IET Circuits Devices Syst., 2012

2011

A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier.

Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta

Microelectron. Reliab., 2011

Electrical performance study of 25 nm Omega-FinFET under the influence of gamma radiation: A 3D simulation.

Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta

Microelectron. J., 2011

Alpha-particle-induced effects in partially depleted silicon on insulator device: With and without body contact.

Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta

IET Circuits Devices Syst., 2011

2010

A proposed DG-FinFET based SRAM cell design with RadHard capabilities.

Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta

Microelectron. Reliab., 2010

Robust Double Gate FinFET Based Sense Amplifier Design Using Independent Gate Control.

Surendra S. Rathod, Ashok K. Saxena, Sudeb Dasgupta

J. Low Power Electron., 2010